Hussam Amrouch - Karlsruhe Institute of Technology, Karlsruhe, Germany
The tutorial will focus on bridging the gap between device physics and the system level towards drawing the impact of steep-slope transistors on computing efficiency and future many-core systems. Therefore, the tutorial will cover both device level and system level. At the device level, both Tunnel FET and Negative Capacitance FET transistors, which are the leading steep-slope transistors will be explained. The inability of MOSFET transistors to switch faster than 60mV/decade, due to the nonscalable Boltzmann factor, is one of the key fundamental limits in physics for technology scaling. This is, in fact, the bottleneck in voltage scaling, which had led to the discontinuation of Dennard’s scaling more than a decade ago. As a result, the operating frequency of processors stopped improving in the last decade to prevent unsustainable on-chip temperatures. Steep-slope transistors are one of the emerging technologies that are rapidly evolving for future lower-power applications. They are able to overcome such a fundamental limit, by offering a sub-threshold swing that goes beyond the fundamental limit. Tunnel FET (TFET) and Negative Capacitance FET (NCFET) are examples of such steep-slope transistor devices. Particularly, NCFET is attracting fast growing attention in both industry and academia.
(1) At the device level: we will explain the underlying the physics that shape steep-slope transistors. We will also demonstrate how improvements in the electrical characteristics of transistors, obtained by a ferroelectric material, can be investigated from physics, where they do originate, all the way up to the system level, where they ultimately affect the efficiency of computing.
(2) At the circuit, architecture and system levels: we will explain how NCFET can revive the prior trends in processor design with respect to voltage and frequency scaling. We will focus on answering the following three key questions: In how far NCFET technology will enable processors (i) to operate at higher frequencies without increasing voltage? (ii) to operate at higher frequencies without increasing power density? and (iii) to operate at lower voltages, while still fulfilling performance requirement? The latter is substantial for IoT devices, where available power budgets are extremely restricted. We will also demonstrate how employing NCFET technology will have a significant impact not only on circuits but also on architecture- and system-level management techniques. For example, as opposed to conventional CMOS technology in which reducing the voltage minimizes the leakage power, NCFET has an inverse dependency. This means that conventional power management techniques will not work any longer since they would lead to suboptimal results depending on system-level workload properties. Such an example and others of the implications at the architectural and system levels will be also discussed during this tutorial talk towards providing the audience with the big picture behind NCFET technology.
Sayeef Salahuddin is the TSMC Distinguished professor of Electrical Engineering and Computer Sciences at the University of California Berkeley. Salahuddin received his B.Sc. in Electrical and Electronic Engineering from BUET (Bangladesh University of Engineering and Technology) in 2003 and PhD in Electrical and Computer Engineering from Purdue University in 2007. He joined the faculty of Electrical Engineering and Computer Science at University of California, Berkeley in 2008. His work has focused on conceptualization and exploration of novel device physics for low power electronic and spintronic devices. Salahuddin has championed the concept of using 'interacting systems' for switching, showing fundamental advantage of such systems over the conventional devices in terms of power dissipation. This led to the discovery of Negative Capacitance Transistors that allows for sub kT/q subthreshold operation in transistors.
Hussam Amrouch is a Research Group Leader at the Chair for Embedded Systems, Karlsruhe Institute of Technology (KIT), Germany. He is leading of the Dependable Hardware research group. He received his Ph.D. degree from KIT in 2015 with distinct (summa cum laude). He has published more than 70 multidisciplinary publications in the major research areas across the computing stack (computer architecture, circuit design and device physics). His key research interests are focused on emerging technologies, embedded systems, computer architecture, low-power design and hardware/software co-design. He received seven times a “European Network of Excellence on High Performance and Embedded Architecture and Compilation” (HiPEAC) Paper Award. He also received three Best Paper Award Nominations for his work in embedded systems reliability; two of them from (DAC’17 and DAC’16) and one from DATE’17.