MONDAY July 20, 10:30am - 12:00pm
Tutorial 3: Prevent Clock Domain Crossings from Breaking Your Chip

Venkatraman Ramakrishnan - Texas Instruments India Pvt. Ltd., Bangalore, India
Sudhakar Surendran - Texas Instruments India Pvt. Ltd., Bangalore, India
Bijitendra Mittra - Cadence Design Systems, Inc., Bangalore, India

The complexity of clocking and reset architecture in current mixed-signal designs, and complexities of dynamic clocking changes with DVFS (Dynamic Voltage & Frequency Scaling) accentuate the criticality of clock domain crossings (CDCs) and reset domain crossings (RDCs). Historically, the industry approach to assessing such crossings has been a structural analysis for synchronization and rudimentary functional checks, with the observations getting dispositioned manually. Comprehension of complex design assumptions in such a manual dispositioning process can often lead to inconsistent assumptions being made, resulting in design bugs. This exposes a need to verify various facets of domain crossings in a systematic fashion.
This tutorial will cover an overview of asynchronous domain crossings, their analysis care-abouts, and comprehensive verification strategies. We start with an introduction to domain crossings, metastability and the need for robust synchronizer design practices, before delving into synchronization schemes and analysis of the effects of metastability on design functionality. We highlight the verification requirements for clock and reset domain crossings, covering signal assumptions, design assumptions and care-abouts of synchronization schemes and interfaces, extending this into functional design scenarios being verified in the presence of metastabilty. We present solutions using both simulation-based and formal verification techniques, bringing out how inconsistencies in the assumptions made during CDC analysis can be avoided. We also highlight scenarios where design analysis can be tuned to ease the overall verification process. We present results from real life designs and show how this approach leads the design practice from CDC/RDC analysis into true design signoff.

Venkatraman Bio: Venkatraman is a Senior Member Technical Staff, Texas Instruments, India, currently working as Senior Technologist in the Connectivity Design team. He has over 19 years of experience in the design and design methodology definition of DSPs and MCUs, focusing on high performance design, low power design strategies and design robustness. He holds 3 patents and has over 50 publications in various international conferences, symposia or EDA design user groups.

Sudhakar Bio: Sudhakar is a Technical lead and Member, Group Technical Staff at Texas Instruments, currently focusing on next generation verification methodologies. For the past 20 year he has worked and led teams on IP verification, SoC verification, mixed-signal verification, emulation, prototyping, and silicon validation. He has more than 25 publications and four patents on verification and micro-architecture.

Bijitendra Mittra Bio: Bijitendra Mittra is working as Senior Principal Product Engineer at Cadence Design Systems. He is a member of the JasperGold Product Engineering team responsible for building the next generation JasperGold apps. He has more than 20 years of experience in EDA and Design Verification. Over the last 13 years, he has been working on formal verification of IPs and SoCs, methodology development and tool development. He has more than 20 publications on Formal Verification. He holds a bachelor’s degree in Electronics & Communication from The Institution of Engineers (India).