MONDAY July 20, 10:30am - 12:00pm
TOPIC AREA: DESIGN, EDA
KEYWORD: LOW POWER, ARCHITECTURE & SYSTEM DESIGN, FRONT END DESIGN
EVENT TYPE: MONDAY TUTORIAL
Tutorial 6: System Level Power Analysis with Unified Power Models

Speakers:
Nagu Dhanwada - IBM Corp., Poughkeepsi, NY
Rhett Davis - North Carolina State Univ., Raleigh, NC
David Ratchkov - Thrace Systems , San Jose, CA
Organizer:
Jerry Frenkil - Silicon Integration Initiative, Inc., Concord, MA

The demand for increased power efficiency in both wired and wireless applications continues to grow unabated. This demand has generated considerable interest in low power design methods that have become well established at the RTL, gate, and physical, levels. While it’s accepted that opportunities for reducing power at the system level are high, low power design automation at the system level has lagged. One primary reason for that lag has been a lack of system level IP block power models, particularly of standardized, inter-operable, models. This has in turn motivated the development of Unified Power Models (UPM), recently standardized as IEEE 2416-2019. This is the first tutorial since the standard’s release in summer 2019. It will address how this new modeling technology is used and the novel, related tools and methodology it enables. This new standard was developed to meet the power modeling needs of three distinct groups of users: IP providers and model producers, system architects and SoC designers, and EDA developers. UPM/2416’s rich semantics facilitate easy and interoperable model exchange by providing four different data representations – scalars, tables, expressions, and contributors (process, voltage, and temperature independent proxies for energy and power)– and three different modeling levels – bit, system, and multi-level. UPM/2416 models also facilitate efficient electro-thermal analysis by providing voltage and temperature independent modeling enabling the late-binding of voltage and temperature values at analysis run time. The tutorial will begin with an overview of the standard. A point of emphasis will be the use of contributors to dramatically reduce model generation costs while at the same time improving the accuracy of SoC analyses with instance specific voltage and temperature conditions. Data consistency from the system level to the gate level will be introduced, showing how UPM/2416 models can be used throughout the design flow.

This overview will be followed by detailed descriptions of the various data representations and modeling levels, elaborating on the applicability of each to different modeling situations. The novel UPM/2416 system level semantics will be illustrated using specific examples of power models for common IP blocks, such as a memory and a RISC-V processor. Bottom-up models, based on design data and power contributors, and top-down models, based on measured or simulated data, will be described in detail. The examples will include details of how UPM/2416 power data models inter-operate with UPF/1801 power state models.

Finally, use of these models will be demonstrated by running live power analyses using emerging UPM/2416 compatible power analysis tools. These demonstrations will focus on new capabilities, such as the late-binding of PVT conditions to the models at analysis run time, mitigating the need for multiple libraries at different PVT combinations. This tutorial is for designers of power and temperature constrained devices and related design automation. It will provide detailed insights into advanced power modeling and analysis techniques using UPM/2416.

Attendees will learn how to develop UPM/2416 power data models, configure them to interoperate with UPF/1801 power state models, and use them with emerging system level power analysis tools.

Jerry Frenkil Bio: Frenkil is the Director of OpenStandards for Si2.  He has over 30 years of experience in the semiconductor and EDA industries as a designer, technologist, entrepreneur, and executive and currently serves as vice-chair of the IEEE P2416 Working Group on System Level Power Modeling.  Jerry co-founded Sente, which later became Sequence Design where he was CTO and VP of R&D.  He has also worked as an independent design consultant and has held management positions at Nanowatt Design, VLSI Technology and Mostek.  Jerry holds a BSEE from the University of Texas, has published over twenty articles including four book chapters on Low Power Design, and holds a dozen patents in circuit design and design automation.

Nagu Dhanwada Bio: Dhanwada is a Senior Technical Staff Member in IBM Systems group, who leads the development of power, reliability, thermal tools and methodologies. He has a PhD in Computer Engineering from University of Cincinnati. He is the chair of the Si2 Low Power Coalition, and the IEEE P2416 power modeling standards committee. He has a corporate award, was named best of IBM in 2015 and has several patents and publications in the areas of low power design, analysis, optimization, modeling, analog design and electronic system level design.

Rhett Davis Bio: Davis is a Professor of Electrical and Computer Engineering at North Carolina State University.  He received B.S. degrees in electrical and computer engineering from North Carolina State University, Raleigh, in 1994 and M.S. and Ph.D. degrees in electrical engineering from the University of California at Berkeley in 1997 and 2002.   He received the National Science Foundation’s Faculty Early Career Development (CAREER) award in 2007. He received the Distinguished Service Award from the Silicon Integration Initiative (Si2) in 2012 for his research in the development of standards for electronic design automation (EDA) and his development of the FreePDK open-source, predictive process design kit.  He works currently with Si2 to develop standards for system-level power-modeling and compact modeling of device reliability.  He has been an IEEE member since 1993 and became a Senior Member in 2011. He has published over 50 scholarly journal and conference articles. He has worked briefly at Hewlett-Packard (now Keysight) in Boeblingen, Germany and consulted for Chameleon Systems, Qualcomm, BEECube, and Silicon Cloud International.
Dr. Davis' research is centered on electronic design automation for integrated systems in emerging technologies.  He is best known for his efforts in design enablement, 3DIC design, thermal analysis, circuit simulation, and power modeling for systems-on-chip and chip multi-processors.

David Ratchkov Bio: Ratchkov has spent 20 years in the semiconductor industry working on all aspects of Power, with most recent focus on modeling, estimation and analysis, optimization and correlation. His career started at LSI Logic and has most recently worked at Broadcom’s Storage Group, before starting his own company Thrace Systems, focused on EDA Tools on Power analysis.