MONDAY July 20, 1:30pm - 3:00pm
Tutorial 10 Part 1: Chiplet Integration: Tools, Methodology, Requirement, Infrastructure

Farhang Yazdani - BroadPak Corp., San Jose, CA
David Kehlet - Intel Corp., Santa Clara, CA
Krishna Settaluri - Blue Cheetah Analog Design, San Francisco, CA
Ramin Farjadrad - Marvell Semiconductor, Inc., Santa Clara, CA
John Park - Cadence Design Systems, Inc., Boulder, CO
Jawad Nasrullah - zGlue Inc., Mountain View, CA
Farhang Yazdani - BroadPak Corp., San Jose, CA

Chiplet design and integration is a new paradigm in semiconductor industry. This tutorial session provides answers to many of the common questions as well as knowledge needed to plan and design chiplet based products. Typical questions about partitioning, die-to-die electrical interface, power delivery, packaging and assembly, substrate requirement, design tool flow and methodology, etc. will be addressed.

Advance packaging technologies play a critical role in enabling chiplet integration. Depending on the chiplet requirements there are number of packaging options available to package chiplets. Common type of packaging technologies such as organic flip chip packages and more advanced technologies such as wafer/panel level fan-out as well as interposer based integration will be presented. We will also present recent advances in interconnects manufacturing technologies necessary to enable seamless integration of fine bump pitch heterogeneous chiplets.

Farhang Yazdani Bio: Yazdani is the President and CEO of BroadPak Corporation. BroadPak is a “key provider of innovative total solution for 2.5D/3D products”. Through his 20 years with the industry, he has served in various technical, management, and advisory positions with leading semiconductor companies worldwide. Farhang is author of the book “Foundations of Heterogeneous Integration: An Industry-Based, 2.5D/3D Pathfinding and Co-Design Approach”. He is the recipient of 2013 NIPSIA award in recognition of his contribution to the advancement and innovations in packaging technologies. He has numerous publications and IPs in the area of 2.5D/3D Packaging and Assembly, serves on various technical committees and is a frequent reviewer for IEEE Journal of Advanced Packaging. He received his undergraduate and graduate degrees in Chemical Engineering and Mechanical Engineering from the University of Washington, Seattle.

Intel/Blue Cheetah Analog Design
Automated Mixed-Signal PHY Generation of the AIB Die-to-Die Interface Porting of the Advanced Interface Bus (AIB) PHY design to different semiconductor processes has been accomplished inside and outside of Intel, and our experience has shown this to require substantial design labor. This is largely due to challenges in designing and verifying analog/mixed signal blocks such as delay cells, level shifters and phase interpolators in new process technologies, and subsequently integrating the blocks within a complete System-On-Chip (SoC). To reduce the design effort of manually porting custom blocks to a new process, Blue Cheetah has developed agile, process portable, and parameterizable generators for the AIB die-to-die interface. The resulting generators produce verified block instances and their respective netlist, GDS, LIB/LEF files, and behavioral models. This session will cover the generator technology, its application to the AIB PHY, the design flow including commercial physical design tools, and the advantages of the automated generator approach.

David Kehlet bio: Kehlet is a researcher at Intel working on pathfinding for FPGA technology including high speed interfaces.  Currently David is focused on die-to-die interfaces to enable a new model of electronic system development.  Earlier at Intel, David was Vice President of IP Engineering, developing communications protocols, signal processing, and memory interfaces on Intel's programmable logic devices. David and his team demonstrated Intel’s first HBM2 controller and the FPGA industry’s first 58Gbps transceiver. David joined Intel in 2015 with the acquisition of Altera Corporation, where he was Vice President of IP and Device Software Engineering since 2011. Earlier he led Altera Technical Services, expanding Altera’s worldwide capability for technical support and building up the company’s FPGA design collateral and customer technical training. David earned BS and MS Electrical Engineering degrees from Stanford University and holds 18 patents in the areas of computer graphics and video.

Krishna Settaluri bio: Settaluri CEO, Blue Cheetah Analog Design received his PhD in electrical engineering from UC Berkeley in December 2018, specializing in the design automation of high speed silicon photonic links using analog generator technology. Krishna has worked at Apple, Google, and Caltech, and has consulted for multiple startups in the past. Prior to his PhD, Krishna received his M.Eng and B.Sc. degrees from MIT in 2012 and 2011, respectively, in electrical engineering and computer science.

Marvell Semiconductor
From SoC to SiP: Solutions for Modular/Heterogeneous IC Design. The semiconductor industry has been facing major challenges in recent years to keep up with the Moore's law to manufacture large and complex SoCs and ASICs, especially in process nodes below 16nm FinFet. In addition, the development cycle and cost in such process node are growing exponentially, due to complex design processes, need for advanced CAD tools, high mask costs to name a few.  This presentation covers the current state of modular/heterogenous system-in-package (SiP) architectures, and the associated die-to-die connectivity solutions, to address these new challenges and enable the industry to produce chips at lower cost, lower time to market with higher reliability.

Ramin Farjadrad bio: Farjadrad, CT & VP of Automotive/Networking PHYs at Marvell, is  in charge of developing multi-GHz connectivity solutions for Autonomous vehicles, Hyperscale data centers, and Enterprise networks. He is also the Chairman of technical committee at Networking for Autonomous Vehicles (NAV) Alliance. Ramin proposed signaling schemes that were adopted as IEEE Standards for 10Gbps Automotive Ethernet and Multi-Gbps Enterprise Ethernet. He has domain expertise in high-speed communication circuits & systems, signal processing, optimized mixed-mode architectures. Ramin is the author of 100+ granted/pending US patents. M.Sc./Ph.D. in EECS from Stanford University. 

Cadence Design Systems
More than Moore Redefines Requirements for Multi-Chiplet Design Tools. IC foundries and OSAT’s are constantly introducing new multi-chip(let) packaging solutions as more fabless semiconductor and systems companies look to SiP as the best alternative to a single monolithic SoC. This trend of “More than Moore” leverages modern packaging technologies and novel approaches to logical partitioning to advance the world of todays multi-chiplet-centric designs. These advancements in package manufacturing solutions combined with new logical partitioning architectures require a modern approach and modern EDA tools to design the next generation multi-chiplet packages. Please join this session if you want to get an understanding of how the Cadence tools and flows are evolving to address the challenges of the next generation of multi-chiplet package designs.

John Park bio: Park brings over 35 years of design and EDA experience to his role as Product Management Group Director for Advanced Semiconductor Packaging at Cadence Design Systems. In this role, John leads a team responsible for defining cross-domain solutions and methodologies for IC, package & PCB co-design and analysis.

Designing heterogeneous chips and systems with chiplets requires special attention to architecture and design methodologies in order to address power dissipation and thermal management.  Power dissipation of chiplets and system components can be modeled at various levels of accuracy, a) based on chiplet area, b) based on datasheets, power draw scenarios and modes of operation, and c) based on detailed circuit-level power description in a format like UPM (IEEE 2416). Chiplets can come from a variety of legacy sources, hence it is likely that only crude models may be available for the purpose of modeling. In such case, power simulations will be based on the typical usage scenario of the device and datasheet-based information.  If complete UPM level description is available for chiplets then vector-based power can be simulated as well. We will use a typical example of a chiplet-based chip to demonstrate a power modeling methodology.  Additionally, advanced power management circuits and methods are needed for active and leakage power control for the chiplets. Active silicon interposers present a unique opportunity for such power management functions. Active interposer can include embedded power management functions such as integrated voltage regulators, DVFS, true power shedding, power metering, and energy throttling for chiplet based systems. With the inclusion of such dynamic control capability, a chiplet based IC could in principle provide superior power performance.

Jawad Nasrullah bio: Dr. Nasrullah is the co-founder and CTO of zGlue Inc, a Silicon Valley technology startup commercially offering chiplet-based designs on active silicon interposers. As an expert in low-power designs for 3D-ICs, Dr. Nasrullah's career has spanned a number of roles at some of the top technology companies including Intel, Sun Microsystems and Transmeta Corporation among others. He earned his Ph.D. in electrical engineering from Stanford University, holds several US patents and is the recipient of a number of national and institutional awards.