THURSDAY July 23, 3:30pm - 5:00pm
TOPIC AREA: IP, DESIGN
KEYWORD: INTERCONNECTS/NETWORKING, EMERGING TECHNOLOGIES
EVENT TYPE: IP TRACK
Will Die-to-Die Interface IP Enable Chiplet-Based Architectures to Finally Achieve Market Success?
Chair:
Raymond Nijssen - Achronix Semiconductor Corp., Santa Clara, CA
Organizer:
Eric Esteve - IP-nest, Sophia, France
Special/Invited Sessions
Die-to-die interface IP technologies enable chiplet-based architectures. Placing multiple die from the same or multiple vendors, or simply partitioning a single SoC to provide acceptable yield, into multiple smaller die with improved yield is now possible. Internally designed chiplets is a technology already adopted in the server, ethernet-switch and FPGA segments. The enabling PHY IP can be parallel with clock forwarded or SerDes based, running at much higher frequencies (up to 112G) than the parallel clock (a few GHz). The optimum solution will need to provide the lowest latency and highest bandwidth while staying energy-efficient. Design requires a low bit error rate (BER) and must be cost-competitive by supporting multi-chip modules on organic substrates rather than more expensive silicon interposers. This session is based on invited papers, given by IP vendors of die-to-die PHYs and chiplet makers describing their proprietary solutions. The audience will learn about this more-than-Moore technology.

Thank you to our IP Track Sponsor:


50.1The Open Domain-Specific Architecture: An Introduction
 Speaker: Bapi Vinnakota - Open Compute Project Foundation, San Jose, CA
 Author: Bapi Vinnakota - Open Compute Project Foundation, San Jose, CA
50.2Co-Optimization of Chiplet Interface and Package Technology
 Speaker: Andy Heinig - Fraunhofer IIS, Institutsteil EAS, Dresden, Germany
 Author: Andy Heinig - Fraunhofer IIS, Institutsteil EAS, Dresden, Germany
50.3Enabling the Next Generation System on Chip
 Speaker: Tony Pialis - AlphaWave IP Corp., Toronto, ON, Canada
 Author: Tony Pialis - AlphaWave IP Corp., Toronto, ON, Canada