MONDAY July 20, 4:00pm - 5:30pm
TOPIC AREA: DESIGN, EDA
KEYWORD: EMERGING TECHNOLOGIES, BACK END DESIGN, ARCHITECTURE & SYSTEM DESIGN
EVENT TYPE: DESIGNER TRACK
Design Challenges and Opportunities in the New Decade
Chair:
Vivek Tiwari - Intel Corp., Santa Clara, CA
Organizer:
Sabya Das - Synopsys, Inc., Sunnyvale, CA
Special/Invited Session
What are the design challenges faced by some of the most cutting-edge design at the latest technology nodes? Designers talk about the real issues that keep them awake at night and solutions they are using to resolve them. In the era of modern designs, system-level architecture varies based on the domain of the targeted application. Hardware architects are developing a high-level design paradigm that enables designers to develop domain-specific architecture. In the context of memory architecture, different design methodologies like FPGA/eASIC/ASIC can be intelligently used to obtain an optimized result. As far as ultra-low-power applications are concerned, deep-learning-based technology at the edge applications can greatly benefit by using adaptive and flexible FPGA architecture In this session, the presenters will discuss various aspects of these technologies, that can be used to solve the state of the art design challenges.

Thank you to our Designer Track Sponsor:


8.1Design Automation Challenges and Opportunities in the Era of AI
 Speaker: Ashish Sirasao - Xilinx Inc., San Jose, CA
 Author: Ashish Sirasao - Xilinx Inc., San Jose, CA
8.2CXL-FPGA Connected Memory and Accelerator Solutions
 Speaker: Bhushan Chitlur - Intel Corp., Hillsboro, OR
 Authors: Bhushan Chitlur - Intel Corp., Hillsboro, OR
Sabyasachi Dey - Intel Corp., Hillsboro, OR
William Li - Intel Corp., Hillsboro, OR
8.3Deep Learning for the Edge with Low Power FPGAs
 Speaker: Nagesh Gupta - Lattice Semiconductor Corp., San Jose, CA
 Author: Nagesh Gupta - Lattice Semiconductor Corp., San Jose, CA