TUESDAY July 21, 1:00pm - 1:45pm
KEYWORD: ANY
EVENT TYPE: RISC-V THEATER
RISC-V Theater: Verification of RISC-V Open ISA processors: New Freedoms in Design Require New and Improved Verification Methodologies
1:00 – 1:15 Imperas Software Ltd, UK
Verification of RISC-V Open ISA processors: compliance is just the starting point, reference model and coverage metrics are key to verification quality
Speakers:
Simon Davidmann, Imperas Software
Lee Moore, Imperas Software
 
1:15 – 1:30 pm OpenHW Group, Canada
Verification of Open RISC-V cores: Adding value to the CORE-V Family of open source processor cores
Speakers:
Rick O’Connor, OpenHW Group
Mike Thompson, Verification Task Group, OpenHW Group
 
1:30 – 1:45 pm Valtrix Systems, India
Verification of RISC-V Open ISA processors – Testing functional correctness for the latest extensions for Bit Manipulation and Vectors.
Speaker:
Shubhodeep Roy Choudhury, Valtrix Systems