TUESDAY July 21, 7:30am - 8:30am
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126.2Novel SIPI Approach for 3DIC Application
 Speaker: Bin Yu - ZTE Corp., Shenzhen, China
 Authors: Bin Yu - ZTE Corp., Shenzhen, China
Jiangtao Zhang - ZTE Corp., Shenzhen, China
Jian Pang - ZTE Corp., Shenzhen, China
Tuobei Sun - ZTE Corp., Shenzhen, China
Zhongming Hou - ANSYS, Inc., Shanghai, China
Shuqiang Zhang - ANSYS, Inc., Shanghai, China
126.3High-Capacity Thermal Power Analysis for Multimillion SoC using Redhawk-SC
 Speaker: Vaishali V. Nair - Xilinx Inc., Hyderabad, India
 Authors: Vaishali V. Nair - Xilinx Inc., Hyderabad, India
Dawn M. Graves - Xilinx Inc., San Jose, CA
Suresh Kumar Varma Mantena - ANSYS, Inc., Bangalore, India
Sankar Ramachandran - ANSYS, Inc., Bangalore, India
126.4Accurate DVD-Aware STA on Potential Critical Paths
 Speaker: Jaeseung Choi - Samsung Semiconductor, Inc., Hwaseong, Republic of Korea
 Authors: Jaeseung Choi - Samsung Semiconductor, Inc., Hwaseong, Republic of Korea
Moon Su Kim - Samsung Electronics Co., Ltd., Suwon, Republic of Korea
Yun Heo - Samsung Electronics Co., Ltd., Hwaseong, Republic of Korea
Jong Pil Lee - Samsung Electronics Co., Ltd., Yongin-City, Republic of Korea
Youngmin Shin - Samsung Electronics Co., Ltd., Hwaseong, Republic of Korea
Vinayakam Subramanian - ANSYS, Inc., Bengaluru, India
Krishnakanth Gilakamsetti - ANSYS, Inc., Bengaluru, India
Vishnu Selvaraj - ANSYS, Inc., Bengaluru, India
126.5First Time Silicon Success Strategy by Enabling Multi-Cycle, Spice-Accurate Dynamic Voltage Drop Analysis in Multi-Die(Chiplets) Foveros-Based Advanced SOC
 Speaker: Biswajit Patra - Intel Corp., Bangalore, India
 Author: Biswajit Patra - Intel Corp., Bangalore, India
126.6Physical Design-Aware IR-Drop Analysis at the Very Early Stage
 Speaker: Dongyoun Yi - Samsung Electronics Co., Ltd., Hwaseong, Republic of Korea
 Authors: Dongyoun Yi - Samsung Electronics Co., Ltd., Hwaseong, Republic of Korea
Byunghyun Lee - Samsung Electronics Co., Ltd., Hwaseong, Republic of Korea
Yongho Lee - Samsung Electronics Co., Ltd., Hwaseong, Republic of Korea
Jongsun Jung - Samsung Electronics Co., Ltd., Hwaseong, Republic of Korea
126.7Vector Profiling Based on Advanced Power Analytics
 Speaker: Girish Deshpande - NVIDIA Corp., Santa Clara, CA
 Authors: Girish Deshpande - NVIDIA Corp., Santa Clara, CA
Emmanuel Chao - NVIDIA Corp., Santa Clara, CA
Kritika Garg - NVIDIA Corp., Santa Clara, CA
Amogh Sakdeo - NVIDIA Corp., Santa Clara, CA
Santosh Santosh - NVIDIA Corp., Santa Clara, CA
Bill Mullen - ANSYS, Inc., San Jose, CA
Yatender Mishra - ANSYS, Inc., San Jose, CA
126.9IP Integration Challenges of Domain-Specific Architectures on Programmable SoC Platforms
 Speaker: Nitin Navale - Xilinx Inc., San Jose, CA
 Authors: Simon Burke - Xilinx Inc., San Jose, CA
Denis Keane - Xilinx Inc., San Jose, CA
Nitin Navale - Xilinx Inc., San Jose, CA
An-Jui Shey - Empyrean Software, San Jose, CA
126.11CATALYST2: Planning Layer Directives for Effective Design Closure
 Speaker: Nancy Y. Zhou - IBM Corp., Austin, TX
 Authors: Nancy Y. Zhou - IBM Corp., Austin, TX
Bijian Chen - IBM Corp., Austin, TX
126.12Power Device Design for High Efficiency Power Converter
 Speaker: Heng-Li Lin - uPI Group Inc., Hsinchu, Taiwan
 Authors: Heng-Li Lin - uPI Group Inc., Hsinchu, Taiwan
Chun-Hao Chen - Huada Empyrean Software Co., Ltd, Hsinchu, Taiwan
Lei Li - Huada Empyrean Software Co., Ltd, Beijing, China
126.13Wire Cost Explorer
 Speaker: Kyungmin Lee - Samsung Electronics Co., Ltd., Hwaseong, Republic of Korea
 Authors: Kyungmin Lee - Samsung Electronics Co., Ltd., Hwaseong, Republic of Korea
Manhwee Jo - Samsung Electronics Co., Ltd., Hwaseong, Republic of Korea
Wooil Kim - Samsung Electronics Co., Ltd., Hwaseong, Republic of Korea
NakHee Seong - Samsung Electronics Co., Ltd., Hwaseong, Republic of Korea
126.14Timing Hold Padding Along Timing Path with Setup Margin Awareness
 Speaker: Patricia C. Fong - Marvell Semiconductor, Inc., Santa Clara, CA
 Author: Patricia C. Fong - Marvell Semiconductor, Inc., Santa Clara, CA
126.16Optimizing Hardware Co-Design of Emerging Memory-Based Analog Computing for AI Inference
 Speaker: Fuxi Cai - Applied Materials, Inc., Santa Clara, CA
 Authors: Fuxi Cai - Applied Materials, Inc., Santa Clara, CA
Christophe Chevallier - Applied Materials, Inc., Sunnyvale, CA
Blessy Alexander - Applied Materials, Inc., Sunnyvale, CA
Apurva Uppala - Applied Materials, Inc., Sunnyvale, CA
She-hwa Yen - Applied Materials, Inc., Sunnyvale, CA
Peter Fu - Applied Materials, Inc., Sunnyvale, CA
Mengzhao Wei - Applied Materials, Inc., Sunnyvale, CA
126.17Verilog AMS Model Development to Enable Mixed Signal Verification
 Speaker: Premkumar Seetharaman - Texas Instruments India Pvt. Ltd., Bengaluru, India
 Authors: Premkumar Seetharaman - Texas Instruments India Pvt. Ltd., Bengaluru, India
Sandeep Punna - SAMSUNG, Bengaluru, India
Lakshmanan Balasubramanian - Texas Instruments India Pvt. Ltd. & IEEE , Bengaluru, India
Swathy Lal - Texas Instruments India Pvt. Ltd., Bengaluru, India
126.18Advanced Analog Behavioral Modeling Technique for Mixed-Signal Verification
 Speaker: Hardik Dipakkumar Parekh - NXP Semiconductors, Bengaluru, India
 Author: Hardik Dipakkumar Parekh - NXP Semiconductors, Bengaluru, India
126.19A Step Towards Zero Silicon Bugs: SVA Protocol-Based Assumption Validation
 Speaker: Rohit K. Sinha - Intel Technology India Pvt. Ltd., Bangalore, India
 Authors: Rohit K. Sinha - Intel Technology India Pvt. Ltd., Bangalore, India
Christie Babu - Intel Technology India Pvt. Ltd. & Intel Corp., Bangalore, India
126.20Novel RTL Power Regression and Minimization Workflow for Mobile GPU Cores
 Speaker: Jiaze Li - Qualcomm Technologies, Inc., Santa Clara, CA
 Authors: Jiaze Li - Qualcomm Technologies, Inc., Santa Clara, CA
Yadong Wang - Qualcomm Technologies, Inc., San Diego, CA
Bagus Wibowo - Qualcomm Technologies, Inc., San Diego, CA
Saurabh Kumar Shrimal - Qualcomm India Pvt. Ltd., Noida, India
Raghu Nagaraj - Qualcomm Technologies, Inc., San Diego, CA
126.21One-Pass Hierarchical CDC Sign-Off with SOC-Level Constraints
 Speaker: Atsunori Machida - Fujitsu Kyushu Network Technologies Ltd., Fukuoka, Japan
 Authors: Katsumi Imamura - Fujitsu Kyushu Network Technologies Ltd., Fukuoka, Japan
Yuji Yoshitani - Fujitsu Kyushu Network Technologies Ltd., Fukuoka, Japan
Atsunori Machida - Fujitsu Kyushu Network Technologies Ltd., Fukuoka, Japan
Akitsugu Nakayama - Fujitsu Kyushu Network Technologies Ltd., Fukuoka, Japan
Takashi Ishikawa - Fujitsu Kyushu Network Technologies Ltd., Fukuoka, Japan
Vikas Sachdeva - Real Intent, Inc., Sunnyvale, CA
Roger Hughes - Real Intent, Inc., Sunnyvale, CA
Kazutaka Kanda - Real Intent, Inc., Sunnyvale, CA
126.22Embedded FPGAs for Field-Programmable ASICs for Dynamic Specialization
 Speaker: Raymond Nijssen - Achronix Semiconductor Corp., Santa Clara, CA
 Authors: Raymond Nijssen - Achronix Semiconductor Corp., Santa Clara, CA
Mike Fitton - Achronix Semiconductor Corp., Santa Clara, CA
126.23Managing a Formal Verification Project from Adoption to Convergence - An IP Manager’s Perspective
 Speaker: Nivin George - Synopsys, Inc., Bangalore, India
 Authors: Nivin George - Synopsys, Inc., Bangalore, India
Venkataraghavan Krishnan - Synopsys, Inc., Mountain View, CA
126.24Silicon Bug Hunt with “Deep Sea Fishing” Formal Verification Methodology
 Speaker: Ping Yeung - Mentor, A Siemens Business, Fremont, CA
 Authors: Ping Yeung - Mentor, A Siemens Business, Fremont, CA
Joe Hupcey III - Mentor, A Siemens Business, Fremont, CA
126.25Novel Tool for Auto-Generating Behavioral Model for AMS Circuits
 Speaker: Yishai A. Statter - Synopsys, Inc., Mountain View, CA
 Authors: Yishai A. Statter - Synopsys, Inc., Mountain View, CA
Yan Zucker - Synopsys, Inc., Mountain View, CA
126.26QKeras: A Package for Heterogeneous Deep Quantization
 Speaker: Claudionor N. Coelho - Google, Inc., Mountain View, CA
 Authors: Claudionor N. Coelho - Google, Inc., Mountain View, CA
Hao Zhuang - Google, Inc., Mountain View, CA
Shan Li - Google, Inc., Mountain View, CA
Raziel N. Alvarez - Google, Inc., Mountain View, CA
Aki N. Kuusela - Google, Inc., Mountain View, CA
126.27Considering Both Power and Clock Designs: A Method For Successful Verification of Power Domain-Aware Clock Domain Crossings
 Speaker: Ashish Amonkar - Cypress Semiconductor Corp., Dublin, CA
 Authors: Ashish Amonkar - Cypress Semiconductor Corp., Dublin, CA
Kurt Takara - Mentor, A Siemens Business, Fremont, CA
126.28Power Consumption Simulation Using the Tools Invented by FortifyIQ
 Speaker: Margit Tritt - FortifyIQ, Inc., Erie, CO
 Authors: Yury Kreimer - FortifyIQ, Inc., Newton, MA
Alexander Kesler - FortifyIQ, Inc., Newton, MA
Yaacov Belenky - FortifyIQ, Inc., Newton, MA
Margit Tritt - FortifyIQ, Inc., Erie, CO
126.29Solving Difficult Formal Verification Problems by Leveraging Formal Algorithms on Industry Application Level
 Speaker: Jian (Jeffrey) Wang - Advanced Micro Devices, Inc., Shanghai, China
 Authors: Jian (Jeffrey) Wang - Advanced Micro Devices, Inc., Shanghai, China
Jia Zhu - Advanced Micro Devices, Inc., Orlando, FL
Ming Fan - Advanced Micro Devices, Inc., Shanghai, China
126.31Late Silicon Bug – Formal Comes to the Rescue
 Speaker: Rohit K. Sinha - Intel Technology India Pvt. Ltd., Bangalore, India
 Author: Rohit K. Sinha - Intel Technology India Pvt. Ltd., Bangalore, India
126.32Formal Verification - Boosting Verification of RTL PPA Optimizations with Sequential Logic Equivalence
 Speaker: Saurabh Kumar Shrimal - Qualcomm India Pvt. Ltd., Noida, India
 Authors: Saurabh Kumar Shrimal - Qualcomm India Pvt. Ltd., Noida, India
Kapil Rajpal - Qualcomm India Pvt. Ltd., Noida, India
Sarbadipta Datta - Qualcomm India Pvt. Ltd., Bangalore, India
Vebjorn Kristensen - Qualcomm Technologies, Inc., San Diego, CA
126.33Effective High-Level Synthesis Flow for ISP Hardware Design Performance and Area Optimization
 Speaker: William Lee - Mentor, A Siemens Business, Seongnam, Republic of Korea
 Authors: William Lee - Mentor, A Siemens Business, Seongnam, Republic of Korea
Jonghyun Bae - SK Hynix, Icheon, Republic of Korea
Honggi Kim - SK Hynix, Icheon, Republic of Korea
126.34Analysis of Faults in Safety Mechanisms and Computation of ISO 26262 Metrics
 Speaker: Jörg Grosse - OneSpin Solutions GmbH, Munich, Germany
 Authors: Jörg Grosse - OneSpin Solutions GmbH, Munich, Germany
Neil Rattray - OneSpin Solutions GmbH, Munich, Germany
126.36A Fast SOC Verification Methodology Using Traffic Monitor and IP-XACT Based Integration Automation
 Speaker: Yonghyun Yang - Samsung Electronics Co., Ltd., Hwaseong, Republic of Korea
 Authors: Yonghyun Yang - Samsung Electronics Co., Ltd., Hwaseong, Republic of Korea
Taejin Kim - Samsung Electronics and Sungkyunkwan Univ., Hwaseong, Republic of Korea
Chul-min Kim - Samsung Electronics Co., Ltd., Hwaseong, Republic of Korea
Hyundon Kim - Samsung Electronics Co., Ltd., Hwaseong, Republic of Korea
Seonil B. Choi - Samsung Electronics Co., Ltd., Hwaseong, Republic of Korea
126.37Security Verification of Xilinx's Root of Trust
 Speakers: Nathan Bolger - Xilinx Inc., San Jose, CA
Nicole Fern - Tortuga Logic, San Jose, CA
 Authors: Nathan Bolger - Xilinx Inc., San Jose, CA
Nicole Fern - Tortuga Logic, San Jose, CA
Jagadish Nayak - Tortuga Logic, San Jose, CA
126.38Heterogeneous Computing SPICE for Analog/Mixed Signal Simulation in High-Performance CPU Design
 Speaker: Jiang Fan - ZHAOXIN Electronic Technology Co. Ltd., Beijing, China
 Authors: Jiang Fan - ZHAOXIN Electronic Technology Co. Ltd., Beijing, China
Zhou Yongqi - ZHAOXIN Electronic Technology Co. Ltd., Beijing, China
Yu Han - Huada Empyrean Software Co., Ltd, Beijing, China
Yang Liu - Huada Empyrean Software Co., Ltd, Beijing, China
126.39Functional Safety Island – As Easy as Palm Trees and Cocktails
 Speaker: Lee C. Harrison - Mentor, A Siemens Business, Little Dunmow, United Kingdom
 Authors: Lee C. Harrison - Mentor, A Siemens Business, Little Dunmow, United Kingdom
Antonio Priore - Arm, Ltd., Cambridge, United Kingdom
126.40Advance Clock-and-Reset Verification of Complex Memory Controller SoCs
 Speaker: Mukesh Panda - Western Digital Corp., Bengaluru, India
 Authors: Mukesh Panda - Western Digital Corp., Bengaluru, India
Sesibhushana Bommana - Western Digital Corp., Bengaluru, India
Amanjit Panda - Western Digital Corp., Bengaluru, India
Vikas Sachdeva - Real Intent, Inc., Sunnyvale, CA
126.42Design Optimization Methodologies to Improve PPA of Automotive SoC
 Speaker: Abhishek Nigam - HCL Technologies Limited, Noida, India
 Authors: Paul Bassett - UHNDER Inc, Austin, TX
Frederick Rush - UHNDER Inc, Austin, TX
Bhanu Prakash - HCL Technologies Limited, Noida, India
Abhishek Nigam - HCL Technologies Limited, Noida, India
Ashwani Gupta - HCL Technologies Limited, Noida, India
Vijay Swarnkar - HCL Technologies Limited, Noida, India
126.43Advanced Power Integrity Flow for NVM IP
 Speaker: Alin Razafindraibe - STMicroelectronics, Grenoble, France
 Authors: Alin Razafindraibe - STMicroelectronics, Grenoble, France
Xavier Lecoq - STMicroelectronics, Grenoble, France
Severine Stemmer - STMicroelectronics, Grenoble, France
126.44Leveraging a Custom Design Database for Timing and PD Analytics
 Speaker: Richard Taggart - IBM Systems Group, Poughkeepsie, NY
 Authors: Richard Taggart - IBM Systems Group, Poughkeepsie, NY
Kerim Kalafala - IBM Systems Group, Poughkeepsie, NY
Nathaniel Hieter - IBM Systems Group, Poughkeepsie, NY
Charles Gates - IBM Systems Group, Poughkeepsie, NY
Hemlata Gupta - IBM Corp., Poughkeepsie, NY
126.45Third-Generation Completeness Analysis of Formal Assertions
 Speaker: Wayne Yun - Advanced Micro Devices, Inc., Markham, ON, Canada
 Author: Wayne Yun - Advanced Micro Devices, Inc., Markham, ON, Canada
126.46Pre-RTL Power Estimation Model Based on Fine-Grained Analytics
 Speaker: Howard Yang - Intel Corp., Vancouver, BC, Canada
 Authors: Howard Yang - Intel Corp., Vancouver, BC, Canada
Andy Wong - Intel Corp. & Univ. of British Columbia, Vancouver, BC, Canada
126.47DFT Architecture for Congestion Resolution in Heavily Abutted Designs
 Speaker: Sreekanth G. Pai - Marvell Semiconductor, Inc., Bangalore, India
 Authors: Sreekanth G. Pai - Marvell Semiconductor, Inc., Bangalore, India
Kelly Ockunzzi - Marvell Semiconductor, Inc., Vermont, VT
Kavitha Shankar - Marvell Semiconductor, Inc., Bangalore, India
126.49Developing a Vendor Independent Web-Based Executable SoC Specification Tool and Workflow
 Speaker: Franz Mayr - Texas Instruments, Inc., Freising, Germany
 Authors: Franz Mayr - Texas Instruments, Inc., Freising, Germany
Maximilian Albrecht - Texas Instruments, Inc., Freising, Germany
Mark Jung - Texas Instruments, Inc., Freising, Germany
126.50Hardware Trojan Detection Tool: Is Your IC Safe?
 Speaker: Shinichi Nagata - Toshiba Information Systems (Japan) Corp., Kawasaki, Japan
 Authors: Shinichi Nagata - Toshiba Information Systems (Japan) Corp., Kawasaki, Japan
Koji Takahashi - Toshiba Information Systems (Japan) Corp., Kawasaki, Japan
Shinichi Kondo - Toshiba Information Systems (Japan) Corp., Kawasaki, Japan
Nobuaki Otsuka - Toshiba Information Systems (Japan) Corp., Kawasaki, Japan
Masaru Oya - Waseda Univ., Tokyo, Japan
Nozomu Togawa - Waseda Univ., Tokyo, Japan
126.51Path-Based Timing Driven Placement Using Iterative Pseudo Netlist Changes
 Speaker: Benjamin Trombley - IBM Corp., Poughkeepsie, NY
 Authors: Benjamin Trombley - IBM Corp., Poughkeepsie, NY
Nathaniel Hieter - IBM Corp., Poughkeepsie, NY
Dan Gay - IBM Corp., Poughkeepsie, NY
126.52AMS Fullchip IR/EM Sign Off Methodology
 Speaker: Sandeep Saini - Synaptics Incorporated, San Jose, California
 Authors: Sandeep Saini - Synaptics Incorporated, San Jose, California
Vikram Muttineni - Synaptics Incorporated, San Jose, CA
126.53Security and Trust Assurance of RISC-V Open-source Cores RocketCore and OpenHW CV32E
 Speaker: Sven Beyer - OneSpin Solutions GmbH, Munich, Germany
 Authors: Blake Buschur - Edaptive Computing, Inc., Dayton, OH
Sven Beyer - OneSpin Solutions GmbH, Munich, Germany
126.54Innovation with Functional Safety Methodologies for Autonomous Vehicles
 Speaker: Itai Yarom - Wave Computing, Mevaseret Zion, Israel
 Author: Itai Yarom - Wave Computing, Mevaseret Zion, Israel
126.55Achieving Superior QoR and Timing Correlation Using Machine Learning Driven Optimization
 Speaker: Jimmy Kim - Samsung Electronics Co., Ltd., Gyeonggi-do, Republic of Korea
 Authors: Jimmy Kim - Samsung Electronics Co., Ltd., Gyeonggi-do, Republic of Korea
Yun Heo - Samsung Electronics Co., Ltd., Hwaseong, Republic of Korea
Jong Pil Lee - Samsung Electronics Co., Ltd., Yongin, Republic of Korea
Youngmin Shin - Samsung Electronics Co., Ltd., Hwaseong, Republic of Korea
Vishal Khandelwal - Synopsys, Inc., Hillsboro, OR
Siddhartha Nath - Synopsys, Inc., La Jolla, CA
Jungbae Park - Synopsys, Inc., Mountain View, CA
Jongon Park - Synopsys, Inc., Seongnam, Republic of Korea
126.56Accelerating Early Design Physical Verification Cycle
 Speaker: Kalyana Kumar A - Advanced Micro Devices, Inc., Bengaluru, India
 Authors: Kalyana Kumar A - Advanced Micro Devices, Inc., Bengaluru, India
Shah Vaishali - Advanced Micro Devices, Inc., Bangalore, India
DE2 Gokul R - Advanced Micro Devices, Inc., Bangalore, India
Nermeen Hossam - Mentor, A Siemens Business, Cairo, Egypt
Bhavani Prasad K - Mentor Graphics (India) Pvt. Ltd., Bangalore, India
126.57Full Chip Voltage Drop Analysis Using Distributed Package Model in Ansys RedHawk
 Speaker: Vivek Trivedi - Astera Labs, Inc., Santa Clara, CA
 Authors: Anil Gutti - ANSYS, Inc., San Jose, CA
Vivek Trivedi - Astera Labs, Inc., Santa Clara, CA
Nate Unger - Astera Labs, Inc., Santa Clara, CA
Jitendra Mohan - Astera Labs, Inc., Santa Clara, CA
126.58VCLP Debug System Fool-Proof VCLP Sign Off
 Speaker: Jebin Mohandas - Intel Technology India Pvt. Ltd., Bangalore, India
 Authors: Jebin Mohandas - Intel Technology India Pvt. Ltd., Bangalore, India
Kanai Ghosh - Intel Technology India Pvt. Ltd., Bangalore, India
Sayan Banerjee - Intel Technology India Pvt. Ltd., Bangalore, India
Prasanth Kurapati - Intel Technology India Pvt. Ltd., Bangalore, India
126.59Dynamic Power Savings at RT Level by Improving Clock Gating Efficiency
 Speaker: Aman Jain - Seagate Technology, LLC, Pune, India
 Author: Aman Jain - Seagate Technology, LLC, Pune, India
126.60Enabling Left-Shift and Comprehensive Verification using Static Signoff Methodologies
 Speaker: Yong Lee - SK hynix Inc., Sungnam, Republic of Korea
 Authors: Yong Lee - SK hynix Inc., Sungnam, Republic of Korea
DongSop Lee - SK hynix Inc., Sungnam, Republic of Korea
Vikas Sachdeva - Real Intent, Inc., Sunnyvale, CA
126.61Using GPU to Accelerate Design Verification of Next-Generation GPU
 Speaker: Ting Ku - NVIDIA Corp., Santa Clara, CA
 Authors: Ting Ku - NVIDIA Corp., Santa Clara, CA
George Kokai - NVIDIA Corp., Santa Clara, CA
Chen Zhao - Empyrean Software, San Jose, CA
126.62Practical Filtering Techniques for Delay Calculating Avoidance in Statistical Timing
 Speaker: Chaitanya Peddawad - IBM India, Bangalore, India
 Authors: Chaitanya Peddawad - IBM India, Bangalore, India
Jeffrey G. Hemmett - IBM Systems and Technology Group, Essex Junction, VT
126.64Block-Level Structured Datapath Placement and Routing: AI Processors Case Study
 Speaker: Aamir Farooqui - Cadence Design Systems, Inc., San Jose, CA
 Authors: Aamir Farooqui - Cadence Design Systems, Inc., San Jose, CA
Vinita Nelson - Cadence Design Systems, Inc., San Jose, CA
Tahrina Ahmed - Cadence Design Systems, Inc., San Jose, CA
126.65Leakage Power Estimation Using Neural Network Models
 Speaker: Howard Yang - Intel Corp., Vancouver, BC, Canada
 Authors: Howard Yang - Intel Corp., Vancouver, BC, Canada
Ali Tariq - Intel Corp. & Univ. of British Columbia, Vancouver, BC, Canada
126.66Fast and Accurate Grid Verification and IR Drop Signoff Methodology for Predictable Path to Tapeout
 Speaker: Hetaswi A. Vankani - Google, Inc., Mountain View, CA
 Authors: Hetaswi A. Vankani - Google, Inc., Mountain View, CA
Sanjay Nilamboor - Google, Inc., Mountain View, CA
Mike Dierickx - Google, Inc., Mountain View, CA
Sreekanth V R - ANSYS, Inc., San Jose, CA
126.67Timing Constraints Integration and Equivalence for Complex SOCs
 Speaker: Subhash Pakki - Xilinx India Technology Services Pvt. Ltd., Hyderabad, India
 Authors: Vinod Kumar Reddy - Xilinx India Technology Services Pvt. Ltd., Hyderabad, India
Pramod Surathkal - Xilinx India Technology Services Pvt. Ltd., Hyderabad, India
Subhash Pakki - Xilinx India Technology Services Pvt. Ltd., Hyderabad, India
126.68Exhaustive Verification of Soc Interconnect Including Conditional and Variable Delays
 Speaker: Udupi Harisharan - Cisco Systems, Inc., San Jose, CA
 Authors: Udupi Harisharan - Cisco Systems, Inc., San Jose, CA
Sai Rama Krishna Nalla - Cisco Systems, Inc., San Jose, CA
Arsen Manukyan - Cisco Systems, Inc., Kanata, ON, Canada
126.69Programming Language Interface (PLI)-Based Disabling of Known Timing Violations in Gate-Level Simulation (GLS) for a Quick Sign Off
 Speaker: Ajay B S - Intel Technology India Pvt. Ltd., Bangalore, India
 Authors: Ajay B S - Intel Technology India Pvt. Ltd., Bangalore, India
Raveendranath Reddy P - Intel Technology India Pvt. Ltd., Bangalore, India
126.70Using Static X-Propagation Sign-Off to Eliminate X-Related Design Bugs
 Speaker: Savitha Raghunath - Palo Alto Networks, Inc., Santa Clara, CA
 Authors: Savitha Raghunath - Palo Alto Networks, Inc., Santa Clara, CA
Guru Shindaghatta - Real Intent, Inc., Sunnyvale, CA
126.72Improving Transition-Coverage Cycle Time with a Declarative Description
 Speaker: Ashish Amonkar - Cypress Semiconductor Corp., Dublin, CA
 Authors: Ashish Amonkar - Cypress Semiconductor Corp., Dublin, CA
Ammar Ahmad - Mentor, A Siemens Business, Fremont, CA
Matthew Ballance - Mentor, A Siemens Business, Wilsonville, OR
126.73Accelerate 5G Chipset Power Integrity Sign Off Using Hierarchical RTL Power Profiling
 Speaker: Chen Lin - ZTE Corp., Shenzhen, China
 Authors: Chen Lin - ZTE Corp., Shenzhen, China
Huafeng Xu - ZTE Corp., Shenzhen, China
Zhongming Hou - ANSYS, Inc., Shanghai, China
126.742.5DIC HBM Chip-Package-System (CPS) Signal Integrity Simulation
 Speaker: Luping Liu - Iluvatar CoreX Inc., Shanghai, China
 Authors: Luping Liu - Iluvatar CoreX Inc., Shanghai, China
Shuqiang Zhang - ANSYS, Inc., Shanghai, China
Rodger Luo - ANSYS, Inc., Shanghai, China
Zhenghao Chu - ANSYS, Inc., Beijing, China
126.76Catching Re-Spin Glitches at Clock Trees, Reset Trees, and CDC Paths
 Speaker: Jebin Mohandas - Intel Technology India Pvt. Ltd., Bangalore, India
 Author: Jebin Mohandas - Intel Technology India Pvt. Ltd., Bangalore, India
126.77Full Chip EMIR Signoff Methodology for ACAP Designs
 Speaker: Srinidhi Raghavan Narasimhan - Xilinx Inc., San Jose , CA
 Authors: Srinidhi Raghavan Narasimhan - Xilinx Inc., San Jose , CA
Piyush Jain - ANSYS, Inc., San Jose, CA
Dawn M. Graves - Xilinx Inc., San Jose, CA
Nitika Marwaha - Xilinx Inc., San Jose, CA
126.78Zetta Hertz Clock Frequency Baud Rate (Zetta Bits per Second- Z.B.P.S.) Speed UART HDL Serial Bus Communication Protocol IP Core
 Speaker: Sastry N. Puranapanda - Silicon Interfaces, Mumbai, India
 Authors: Sastry N. Puranapanda - Silicon Interfaces, Mumbai, India
Avnita Pal - Silicon Interfaces, Mumbai, India
126.79Efficient and Cost-Effective EDA Environment Built Easily in the AWS Cloud
 Speaker: Nipur Bhonge - ClioSoft, Inc., Fremont, CA
 Authors: Mark Duffield - Amazon Web Services, Inc., Fremont, CA
Jessica Tandel - Amazon Web Services, Inc., Fremont, CA
Simon Rance - ClioSoft, Inc., Fremont, CA
Nipur Bhonge - ClioSoft, Inc., Fremont, CA
126.80Design Aware Bounded Timing Liberty Generation Methodology for IP-SOC Co-Development
 Speaker: Bindu P. Rao - Intel Technology India Pvt. Ltd., Bangalore, India
 Authors: Bindu P. Rao - Intel Technology India Pvt. Ltd., Bangalore, India
Anubhav Shukla - Texas Instruments, Inc., Bangalore, India
126.81Cross Products Hotspot Detection with Calibre SONR: A Machine Learning Technique
 Speaker: Haizhou Yin - GLOBALFOUNDRIES, Malta, NY
 Authors: Haizhou Yin - GLOBALFOUNDRIES, Malta, NY
Yuansheng Ma - Mentor, A Siemens Business, Fremont, CA
Qian Xie - GLOBALFOUNDRIES, Malta, NY
Shaowen Gao - GLOBALFOUNDRIES, Malta, NY
Juli Opitz - Mentor, A Siemens Business, Fremont, CA
Rui Wu - Mentor, A Siemens Business, Wilsonville, OR
Le Hong - Mentor, A Siemens Business, Wilsonville, OR
Liang Cao - Mentor, A Siemens Business, Fremont, CA
Dingyi Hong - Mentor, A Siemens Business, Fremont, CA
Joerg Mellmann - Mentor, A Siemens Business, Wilsonville, OR
Panneerselvam Venkatachalam - GLOBALFOUNDRIES, Malta, NY
Yuyang Sun - Mentor, A Siemens Business, Wilsonville, OR
James Word - Mentor, A Siemens Business, Wilsonville, OR
126.82Confronting Embedded Security before it Confronts You
 Speaker: Chris Shore - Arm, Ltd., Cambridge, United Kingdom
 Author: Chris Shore - Arm, Ltd., Cambridge, United Kingdom
126.83The Role of Equivalence Checking for FPGAs in Nuclear Applications
 Speaker: Juergen Dennerlein - Framatome, Erlangen, Germany
 Author: Juergen Dennerlein - Framatome, Erlangen, Germany
126.85A Novel PI Sign-Off Flow with Better Coverage in Sub-7nm Chip Designs
 Speaker: Chen Junjie - Sanechips Co., Ltd., Xi'an, China
 Authors: Chen Junjie - Sanechips Co., Ltd., Xi'an, China
Ouyang Keqing - Sanechips Co., Ltd., Shenzhen, China
Chang Zhao - ANSYS, Inc., Shanghai, China
Xin Yao - ANSYS, Inc., Shanghai, China
126.86Hardware Implementation of Convolutional Neural Network layers
 Speaker: Satheesh Appukuttan - Broadcom Corp., Irvine, CA
 Authors: Satheesh Appukuttan - Broadcom Corp., Irvine, CA
Tara Keigharn - Raytheon Company, El Sugundo, CA
126.88Single Definition to Rule Them All
 Speaker: Jigar Savla - Recogni & Georgia Institute of Technology, Sunnyvale, CA
 Author: Jigar Savla - Recogni & Georgia Institute of Technology, Sunnyvale, CA
126.89Novel Methodology to Reduce Inaccuracies in Vectorless Power Estimation
 Speaker: Subhechcha Banerjee - Marvell Semiconductor, Inc., Bengaluru, India
 Authors: Subhechcha Banerjee - Marvell Semiconductor, Inc., Bengaluru, India
Rahul Kataria - Marvell Semiconductor, Inc., Bengaluru, India
Kushal Kamal - Marvell Semiconductor, Inc., Bengaluru, India
126.90Efficient Secondary Power Routing Strategy for Ultra Low Power and Low Cost Designs
 Speaker: Aswani Kumar Golla - Texas Instruments India Pvt. Ltd., Bangalore, India
 Authors: Aswani Kumar Golla - Texas Instruments India Pvt. Ltd., Bangalore, India
Richa Shrivastava - Texas Instruments India Pvt. Ltd., Bengaluru, India
Pankaj Dhingra - Texas Instruments India Pvt. Ltd., Bengaluru, India
Venkatraman Ramakrishnan - Texas Instruments India Pvt. Ltd., Bangalore, India
Gaurav K. Varshney - Texas Instruments India Pvt. Ltd., Bangalore, India
Penchalkumar Gajula - Texas Instruments India Pvt. Ltd., Bengaluru, India
Ayaskanta Behera - Texas Instruments India Pvt. Ltd., Bengaluru, India
126.92Rapid Adoption of Full-Chip Hierarchical CDC Analysis
 Speaker: Leo Butler - Cisco Systems, Inc., San Jose, CA
 Authors: Leo Butler - Cisco Systems, Inc., San Jose, CA
Kurt Takara - Mentor, A Siemens Business, Fremont, CA
126.93Efficient Methodology for Smart Digital Grid and Clock Tree Implementation of Automotive SoC
 Speaker: Abhishek Nigam - HCL Technologies Limited, Noida, India
 Authors: Abhishek Nigam - HCL Technologies Limited, Noida, India
Paul Bassett - UHNDER Inc, Austin, TX
Brian Arnold - UHNDER Inc, Austin, TX
Nilotpal Arjun - HCL Technologies Limited, Noida, India
126.94HDL Implementation of Tera, Peta, Exa, Zetta, Yotta, Geopt, Bronto Bytes RAM SOC Design
 Speaker: Sastry N. Puranapanda - Silicon Interfaces, Mumbai, India
 Authors: Sastry N. Puranapanda - Silicon Interfaces, Mumbai, India
Shikhadevi S. Katharia - Silicon Interfaces, Mumbai, India
126.95Methodology Abstracting Functional Behavior into Statistical Activity Framework to Allow Using in the Vectorless Power Analysis for Automotive SoC
 Speaker: Abhishek Nigam - HCL Technologies Limited, Noida, India
 Authors: Paul Bassett - UHNDER Inc, Austin, TX
Brian Arnold - UHNDER Inc, Austin, TX
Abhishek Nigam - HCL Technologies Limited, Noida, India
Bhanu Prakash - HCL Technologies Limited, Noida, India
Rishabh Banerjee - Qualcomm India Pvt. Ltd., Noida, India
126.96A Novel Approach to Hunt for Bugs in an Algorithmic Design: Exploiting Formal Verification
 Speaker: Navarshi Dhiman - NXP Semiconductors, Faridabad, India
 Authors: Navarshi Dhiman - NXP Semiconductors, Faridabad, India
Tejbal Prasad - Cadence Design Systems, India Pvt. Ltd., Greater Noida, India
Gaurav Gupta - NXP Semiconductors, Noida, India
126.97Efficient and Cost-Effective EDA Environment Built Easily in the Google Cloud
 Speaker: Jhilam Bishwas - Google, Inc., Fremont, CA
 Authors: Jhilam Bishwas - Google, Inc., Fremont, CA
Cori Peele - Google, Inc. & Cadence Design Systems, Inc., Mountain View, CA
Simon Rance - ClioSoft, Inc., Fremont, CA
126.98Fast and Accurate Modeling of Voltage Drop Impact on Timing
 Speaker: Sesha Sai Jyothi Kolli - NVIDIA Corp., Santa Clara, CA
 Authors: Sesha Sai Jyothi Kolli - NVIDIA Corp., Santa Clara, CA
Santosh Santosh - NVIDIA Corp., Santa Clara, CA
Vinayakam Subramanian - ANSYS, Inc., San Jose, CA
Vishnu Raj - ANSYS, Inc., San Jose, CA
126.99Targeted Area Recovery in Signoff Timing
 Speaker: Greg Ford - Marvell Semiconductor, Inc. & GLOBALFOUNDRIES, Santa Clara, CA
 Author: Greg Ford - Marvell Semiconductor, Inc. & GLOBALFOUNDRIES, Santa Clara, CA
126.100Novel GUI-Based UVM Template Builder
 Speaker: Vignesh Manoharan - Intel Corp., San Jose, CA
 Author: Vignesh Manoharan - Intel Corp., San Jose, CA