TUESDAY July 21, 1:30pm - 3:00pm
TOPIC AREA: EDA, DESIGN
KEYWORD: LOW POWER, VERIFICATION/VALIDATION, ARCHITECTURE & SYSTEM DESIGN
EVENT TYPE: DESIGNER TRACK
Advanced Power Techniques/RISC-V Design and Validation
Chair:
Dave Rich - Mentor, A Siemens Business
Power consumption continues to be a critical issue in any modern design. The first half of this session will present a variety of new techniques related to low-power design and validation. Another topic that has taken the industry by storm in recent years is the revolutionary open-source RISC-V ISA. In the second half of this session, we will discuss some new ideas in design and validation related to this architecture.

Thank you to our Designer Track Sponsor:


27.1Making Learning-Based Power Modeling Possible for Complex Designs and Applications
 Speaker: Caaliph Andriamisaina - CEA-LIST: Lab. for Integration of Systems and Technology, Gif-sur-Yvette, France
 Authors: Caaliph Andriamisaina - CEA-LIST: Lab. for Integration of Systems and Technology, Gif-sur-Yvette, France
Pierre-Guillaume Le Guay - CEA-LIST: Lab. for Integration of Systems and Technology, Gif-sur-Yvette, France
Kods Trabelsi - CEA-LIST: Lab. for Integration of Systems and Technology, Gif-sur-Yvette, France
Tanguy Sassolas - CEA, Gif-sur-Yvette, France
Julien Legriel - Synopsys, Inc., Grenoble, France
27.2Advanced Low-Power Retention Simulation Framework
 Speaker: Lakshmanan Balasubramanian - Texas Instruments India Pvt. Ltd. & IEEE , Bengaluru, India
 Authors: Lakshmanan Balasubramanian - Texas Instruments India Pvt. Ltd. & IEEE , Bengaluru, India
Prachi Mishra - Texas Instruments India Pvt. Ltd., Bengaluru, India
Sushmitha T G - KarMic Design Pvt. Ltd. & Texas Instruments India Pvt. Ltd., Udupi, India
Aswanikumar Golla - Texas Instruments India Pvt. Ltd., Bengaluru, India
Venkatraman Ramakrishnan - Texas Instruments India Pvt. Ltd., Bangalore, India
Vivek Gandhi - Texas Instruments India Pvt. Ltd., Bengaluru, India
Parthasarathy Ramesh - Texas Instruments India Pvt. Ltd., Bengaluru, India
Manash Ranjan Raiguru - Cadence Design Systems, India Pvt. Ltd., Bengaluru, India
27.3Simplifying Hierarchical Low-Power Designs Using Hard IP Power Models in Intel Design
 Speaker: Rohit K. Sinha - Intel Technology India Pvt. Ltd., Bangalore, India
 Author: Rohit K. Sinha - Intel Technology India Pvt. Ltd., Bangalore, India
27.4RISCV-DV: An Open Source Verification Platform for RISC-V Processors
 Speaker: Tao Liu - Google, Inc., Mountain View, CA
 Authors: Tao Liu - Google, Inc., Mountain View, CA
Richard Ho - Google, Inc., Mountain View, CA
27.5A RISC-V Secure Element for PQC: “Fantasy Chip” Codesign Approach
 Speaker: Markku-Juhani O. Saarinen - PQShield, Oxford, United Kingdom
 Author: Markku-Juhani O. Saarinen - PQShield, Oxford, United Kingdom
27.6Cyber Escort Unit: A Unique Solution to Ensure Security and Safety in Code Execution for the Automotive Market
 Speaker: Sylvain Guilley - Secure-IC SAS, Paris, France
 Authors: Sylvain Guilley - Secure-IC SAS, Paris, France
Michel Le Rolland - Secure-IC SAS, Cesson-Sevigne, France