MONDAY July 20, 1:30pm - 3:00pm
TOPIC AREA: EDA, DESIGN
KEYWORD: VERIFICATION/VALIDATION, FRONT END DESIGN, EMERGING TECHNOLOGIES
EVENT TYPE: DESIGNER TRACK
New Frontiers in Formal, Static, and UVM-Based Verification
Chair:
Achutha Kirankumar V M - Intel Corp., Bangalore, India
Formal and static methods continue to be a critical and growing part of verification. The first half of this session will present new techniques in this area for deadlock verification, finite state machine checks, and reset domain crossing (RDC) challenges.
However, simulation continues to be a critical lynchpin of our validation strategies. The second half of this session will present some new ideas for effective UVM-based simulation.
Thank you to our Designer Track Sponsor:
| 4.1 | Easy Deadlock Verification and Debug with Advanced Formal Verification | |
| Speaker: | Laurent Arditi - Arm, Ltd., Valbonne, France |
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| Authors: | Laurent Arditi - Arm, Ltd., Valbonne, France Vincent Abikhattar - Arm, Ltd., Sophia-Antipolis, France Joe Hupcey III - Mentor, A Siemens Business, Fremont, CA Jeremy Levitt - Mentor, A Siemens Business, Fremont, CA |
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| 4.2 | Robust FSM Verification Aspects – A Formal Methodology | |
| Speaker: | Abhinav Parashar - Texas Instruments India Pvt. Ltd., Bengaluru, India |
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| Authors: | Abhinav Parashar - Texas Instruments India Pvt. Ltd., Bengaluru, India Pooja S. Bhat - Texas Instruments India Pvt. Ltd., Bengaluru, India Harish Maruthiyodan - Texas Instruments India Pvt. Ltd., Bangalore, India |
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| 4.3 | Innovative Techniques to Solve Complex RDC Challenges | |
| Speaker: | Rohit K. Sinha - Intel Technology India Pvt. Ltd., Bangalore, India |
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| Author: | Rohit K. Sinha - Intel Technology India Pvt. Ltd., Bangalore, India |
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| 4.4 | Achieve Better Communication in Your UVM TB Using These Obscure UVM Classes | |
| Speaker: | Pavan Yeluri - NVIDIA Corp., Hyderabad, India |
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| Authors: | Pavan Yeluri - NVIDIA Corp., Hyderabad, India Ranjith Nair - NVIDIA Corp., Hyderabad, India |
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| 4.5 | A Novel Methodology Applying Dynamic Save and Restart to SOC Verification | |
| Speaker: | Jicheon Kim - Samsung Electronics Co., Ltd., Hwaseong, Republic of Korea |
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| Authors: | Jicheon Kim - Samsung Electronics Co., Ltd., Hwaseong, Republic of Korea Minjae Kim - Samsung Electronics Co., Ltd., Hwaseong, Republic of Korea Daewoo Kim - Samsung Electronics Co., Ltd., Hwaseong, Republic of Korea Seonil B. Choi - Samsung Electronics Co., Ltd., Hwaseong, Republic of Korea |
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| 4.6 | UVM VIP Test Intent Reuse from IP to Sub System and SOC Using Portable Stimulus | |
| Speaker: | Sastry N. Puranapanda - Silicon Interfaces, Mumbai, India |
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| Authors: | Sastry N. Puranapanda - Silicon Interfaces, Mumbai, India Priyanka Gharat - Silicon Interfaces, Mumbai, India Kiran Malvi - Silicon Interfaces, Mumbai, India |
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