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Video Results for 48th DAC (2011)

6.1 Dimetrodon: Processor-Level Preventive Thermal Management via Idle Cycle Injection

6.2 Dynamic Thermal Management for Multimedia Applications Using Machine Learning

6.3 Improved Post-Silicon Power Modeling Using AC Lock-In Techniques

6.4 Thermal Signature: A Simple Yet Accurate Thermal Index for Floorplan Optimization

8.1 Scalable Parts Families, Context, and Computational Design for Gene Expression Engineering

8.2 Gene and Cellular Circuit Design

8.3 A Verifying Compiler for DNA Chemical Reaction Networks

12.1 TSV Stress-Aware, Full-Chip Mechanical Reliability Analysis and Optimization for 3-D IC

12.2 Hybrid Modeling of Non-Stationary Process Variations

12.3 Efficient SRAM Failure Rate Prediction via Gibbs Sampling

12.4 Direct Matrix Solution of Linear Complexity for Surface Integral Equation-Based Impedance Extraction of High Bandwidth Interconnects

18.1 MUSTARD: A Coupled, Stochastic-Deterministic, Discrete-Continuous Technique for Predicting the Impact of Random Telegraph Noise on SRAMs and DRAMs

18.2 Fast, Non-Monte-Carlo Transient Noise Analysis for High-Precision Analog/RF Circuits by Stochastic Orthogonal Polynomials

18.3 Automatic Stability Checking for Large, Linear Analog Integrated Circuits

18.4 Performance Bound Analysis of Analog Circuits Considering Process Variations

18.5 Rethinking Memory Redundancy: Optimal Bit Cell Repair for Maximum-Information Storage

18.6 Programmable Analog Device Array (PANDA): A Platform for Transistor-Level Analog Reconfigurability

19 EDA Research: Stalled, Driving in Circles, or Running out of Gas?

24.1 Leakage-Aware Redundancy for Reliable Subthreshold Memories

24.2 A 40nm Inverse Narrow-Width, Effect-Aware Subthreshold Standard Cell Library

24.3 Layout-Aware, Line-Edge Roughness Modeling and Poly-Optimization for Leakage Minimization

24.4 Post Sign-Off Leakage Power Optimization

25 Software-Hardware Verification Battle: Prototyping vs. Emulation

31 The Billion Dollar Question: How to Verify Billion-Gate Designs

37 ESL HW/SW Verification: A Reality Check

43 Double Trouble or Double Your Fun: Double-Patterning and Variability

49 Parallel or Paralyzing: Is Parallel EDA Worth the Trouble?

CONVENED THURSDAY, June 09, 2011, 4:00 PM - 6:00 PM
VIDEO: SESSION 49
TOPIC AREA: GENERAL INTEREST

PANEL: Parallel or Paralyzing: Is Parallel EDA Worth the Trouble?

Chair:

Giovanni De Micheli - Ecole Polytechnique Fédérale de Lausanne, Lausanne, Switzerland

Organizer:

Wolfgang Rosenstiel - Univ. Tübingen, Tuebingen, Germany

The advent of ubiquitous multicore processors has made parallelization of EDA software an attractive proposition. The reality has been anything but that. As it turns out, it is REALLY hard! These panelists explain what it takes to parallelize real applications and where parallelization is a dead end.

Speakers:

Patrick Madden - SUNY Binghamton, Binghamton, NY
Dipanjan Gope - Physware, Inc., Mountain View, CA
Guy Maor - Extreme DA Corp., Santa Clara, CA
Peng Li - Texas A&M Univ., College Station, TX
Bor-Yiing Su - Univ. of California, Berkeley, CA
Andrei Vladimirescu - Univ. of California, Berkeley, CA