TOPIC AREA: USER TRACK
In this unique dual-keynote, the design process at two leading companies will be discussed.The speakers will cover key challenges, engineering decisions and design methodologies to achieve top performance and turn-around time. The presentations describe where EDA meets practice under the most advanced nodes, so will be of key interest to both designers and EDA professionals alike.
POWERTM Processor Design and Methodology Directions: Joshua Friedrich
Processor designs and the EDA tools that support them stand at a key inflection point. The era of Dennard scaling and exponential single thread performance growth is a distant memory. Multi-thread performance continues to grow. However, the gain from simply adding more cores to a die by stepping to the next process node is diminishing due to technology challenges, application bottlenecks, and power/packaging constraints. To continue to deliver the cost-performance gains that drive our industry, designers will need to bring significant innovation to bear by integrating heterogeneous system components and accelerating key portions of the software stack in hardware. This transformation from technology-driven design to innovation-driven design defines new priorities for EDA development compared to prior eras. While timing optimization, power reduction, and support for modular designs remain necessary, differentiation will be achieved by enabling designer productivity through technology simplification, design abstraction, and robust support for heterogeneous IP.
Designing a 22nm Intel® Architecture Multi-CPU and GPU: Brad Heaney
With each new process technology node and integration of more system components on to a monolithic die, the design methodology challenges must advance to enable validation and implementation of these complex products. With Intel’s new 22nm technology, we are designing products with over 1.4 billion transistors and integrating hardware blocks that naturally want different process and design optimizations. The recently launched 3rd Generation Intel® Core Process (codename Ivy Bridge) has an integrated Graphics Processing Unit that has different process and design demands than the CPU Core Processor. With the size and diversity of the product hardware, combined with new advanced process technology features, such as Intel’s new tri-gate transistor, more capabilities for silicon debug, coverage, and manufacturing need to be planned and incorporated into the architecture and design implementation. By close collaboration between the process development and design teams at Intel, we are able to develop design methods to ramp these large, complex products into high volume manufacturing at, or ahead of, the schedule on prior products.
Joshua Friedrich is a Senior Technical Staff Member and Senior Manager of POWERTM Technology Development in IBM’s Server and Technology Group. In his role, Josh leads the physical design, technology direction, and methodology of IBM’s future POWERTM processors. Josh has been part of the POWER development team since POWER4TM, and on past POWERTM designs, Josh has led multiple design disciplines including power estimation and reduction, hardware characterization, memory subsystem circuit development, and core execution units. Before joining IBM, Josh received his Bachelor of Science in Electrical Engineering from the University of Texas at Austin.
Brad Heaney is an Intel® Architecture Group Project Manager and operates out of Intel’s Folsom Design Center. Brad is a 25 year veteran at Intel and started his career working on the design of the 80386 family of CPUs and is the holder of four patents for his design work. In the last few years, Brad has been managing the teams that deliver Intel’s lead vehicles for ramping new process technologies. Brad’s team developed the Penryn CPU, which was a lead vehicle for 45nm process technology. In April of this year, they launched the Ivy Bridge CPU (3rd Generation Intel® Core Processor), which is the lead vehicle for Intel’s 22nm process technology. Brad received his Bachelor of Science degree from Drexel University in Philadelphia and his Master of Science in Electrical Engineering degree from Stanford University prior to joining Intel.
Brad Heaney - Intel Corp., Folsom, CA