CONVENED WEDNESDAY, June 05, 2013, 11:25 AM - 12:15 PM
TOPIC AREA: DESIGNER TRACK
KEYNOTE: Designing Mobile Communications SoCs: Handhelds to Infrastructure
The Designer Keynote features leaders from two leading companies in the global wireless communications industry. Scott Runner (Qualcomm) will discuss the interplay between silicon design, power, software, and verification for handheld communications and computing SOCs. Sanjive Agarwala (Texas Instruments) will overview design challenges and solutions for high-performance wireless infrastructure systems. The Designer Keynote will be followed in the afternoon by a special question/answer panel session with Sanjive, Scott, and leads from their design teams.
Design and Methodology of Wireless ICs for Mobile Applications: True SoCs Have Come of Age - J. Scott Runner
Today’s advanced Systems on a Chip (SoC) for mobile applications are the confluence of high performance CPUs, DSPs, multiple air standard modems for WWAN, WLAN and WPAN, GPS, high end graphics, video and audio CODECs, a variety of peripherals, high speed memory and security and power management technologies on one SoC or SiP. Adding RF, PMIC and DDR memory and you truly have a complete system. Designing such devices marries multiple disciplines of digital and mixed signal HW, SW, systems, design, verification, packaging, physical design engineers and many others. Doing so in the time frames required to satisfy the appetites of smartphone and tablet customers, while delivering to cost, power, performance and quality targets demands novel approaches in design methodology. We will explore methodologies to address HW-SW co-design, power and design verification and validation in the design of the most popular device in the wireless world.
Infrastructure Embedded Processing Systems – Trends and Opportunities - Sanjive Agarwala
The increasingly connected world has created an explosive growth in content creation, distribution and consumption. Embedded systems for infrastructure equipment to handle the content such as wireless base stations, multimedia and video servers, purpose-built servers, medical imaging, and mission critical applications have made great strides in offering unparalleled scale of integration and complete system solutions. Innovations in system and design automation, and semiconductor processing have enabled the industry to deliver flexible and scalable architectures which operators are able to adapt and deploy quickly at impressive cost and performance points.
In this talk we will take a closer look at the evolution of the wireless infrastructure market and the enabling system solutions. Wireless operators are seeking cost-effective, high-performance solutions that meet the demands of user traffic today, and position their network architecture for the increased demands of the future. These systems require low-power, high-performance DSP and RISC multicore processing flexibility along with application-specific acceleration, packet processing, networking infrastructure and high bandwidth interfaces all integrated on a single multi-billion transistors Systems-on-Chip. This is all delivered with scalable system architecture in leading-edge semiconductor technologies and software to build complete system solutions. We will examine the progress so far, the trends and opportunities to continue offering value and differentiation to the market.
is currently the Vice President of Advanced Methdologies and Low Power Design at Qualcomm Technologies, Inc. He has worked in engineering in the semiconductor and EDA industries for 30 years, holding positions as Director of processors and IP, Design Automation and design manager at Conexant Systems Inc., a “founding” member of the DesignWare team at Synopsys Inc., and DSP and ASIC design engineer and Design Center manager at Fujitsu Microelectronics. He has taped out over 48 devices and has authored over 22 papers & articles. He holds a B.S. in Physics with emphasis in Computer Science and EE from Georgia Tech.
J. Scott Runner - Qualcomm Technologies, Inc., San Diego, CA
is a TI Fellow and Director of WW Silicon Development in Processor Business at Texas Instruments. He leads the worldwide development of leading edge SoCs in Communication Infrastructure, Multi-Core DSP, Automotive and Industrial markets at TI. He is also responsible for the roadmap and development of TI C6x DSP core. These arrays of innovative high performance and low power systems are designed in leading edge process technologies with state of the art tools, flows and methodologies. He has worked on a number of generations of high performance DSP/RISC Systems at TI.
Sanjive earned a Master of Science degree in Computer Science in 1989 from Southern Methodist University in Dallas, TX. He also has a Bachelor degree in Electrical Engineering from Punjab Engineering College in India. He is a member of IEEE.
Sanjive Agarwala - Texas Instruments, Inc., Dallas, TX