Exhibitor Forum

Monday, June 14, 2010

Time: 2:00 PM — 4:00 PM

Location: Exhibit Hall B - Booth #1562

Summary:

• Cadence Design Systems, Inc.: 2:00-2:35pm
• Real Intent, Inc.: 2:40-3:15pm
• FishTail Design Automation, Inc.: 3:20-3:55pm

Cadence Design Systems, Inc.: Solutions for IP Exploration and Integration

Utilizing both external and internal IP and design reuse in SoC development is central to reducing cost and risk. However, the selection and integration of IP introduces many new challenges that potentially add to design cost and risk in unexpected ways. In this presentation we will examine these challenges and discuss ways in which they can be avoided and managed.

Speaker:

Neil Hand - Cadence Design Systems, Inc., San Jose, CA

Real Intent, Inc.: Efficient and Practical Prevention of X-Related Bugs

It is painful and time consuming to identify X sources and chase their propagation between RTL and Gate representations. Such "X-Prop" issues often lead to a dangerous masking of real bugs. No clear solution has existed thus far to address this problem effectively. This presentation explains the common sources of X's and shows how they can cause functional bugs. It then discusses the challenges that Real Intent has overcome in developing an efficient solution to assist designers in catching bugs caused by X propagation and ensuring X-robust designs.

Speaker:

Oren Katzir - Real Intent, Inc., Sunnyvale, CA

FishTail Design Automation, Inc.: Formal Verification of Multi-Cycle Paths on SOCs

Multi-cycle paths are routinely used to meet area, power and timing objectives on high-performance designs. Frequently, however, these constraints are specified incorrectly, either because they apply to paths where they should not, or because there simply is no multi-cycle behavior because of a design bug. Catching these mistakes early is key to silicon success. Failure to do so has serious ramifications - silicon failure, schedule slip. We present a flow for the scalable verification of MCPs on large designs, with an intuitive debug environment and a goal of 100% signoff prior to tapeout.

Speaker:

Ajay Daga - FishTail Design Automation, Lake Oswego, OR