System-level Power Distribution Noise Closure: Looking Beyond the SoC Power Integrity Challenge
Thursday, April 1, 2010
By: Aveek Sarkar / Apache Design Solutions
Topic:
General
— Sub-topic:
No Topic
Tags: Power grid noise, power optimization, PDN design and fixing, system-level design
SummaryThis article takes a comprehensive look at the subject of power, and reviews its
various facets, such as power estimation and optimization, power grid noise prediction, power
delivery network design and power-induced failure mechanisms, both on the die and in the
system. Through the use of various examples of prior work done and to be presented in DAC
2010, this article attempts to tie together all these seemingly disparate topics into an integrated
topic of system-level noise modeling, whose challenges confront IC, package and PCB
engineers as they consolidate ever-increasing functionality requirements in their designs
through advanced circuit, layout and processing technologies.
Download PDF
All general topics
|