Feb 2, 2012
Campbell, Calif.– February 2, 2012 – Silicon Frontline Technology, Inc. (SFT), an Electronic Design Automation (EDA) company in the post-layout verification market, announced today that X-FAB Silicon Foundries has used SFT’s R3D (Resistive 3D) software for X-FAB’s 0.18 micrometer high-voltage process (XH018), providing improvements in reliability and efficiency. X-FAB is the world's leading foundry group for More-than-Moore semiconductor applications.
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Jan 27, 2012
LOUISVILLE, Colo. – January 27, 2012 – The Design Automation Conference (DAC), the premier conference devoted to design and design automation of electronic systems (EDA), is now accepting nominations for the Marie R. Pistilli Women in EDA Achievement Award. The 49th DAC will be held at the Moscone Convention Center, San Francisco, June 3rd -7th 2012. Nominations must be received no later than 5 PM, MST, Friday, March 9th, 2012.
This annual award, named for Marie R. Pistilli, the former organizer of DAC, recognizes individuals who have visibly helped to advance the profile of women in the EDA industry. This year’s honoree (to be announced prior to DAC) will be interviewed and presented with the award at the conference during the Pavilion Panel: A Conversation with the 2012 Marie R. Pistilli Award Winner on June 4th, 2012.
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Jan 17, 2012
SANTA CLARA, CA, —January 17, 2012— Berkeley Design Automation, Inc., provider of the world’s fastest nanometer circuit verification, today announced that Triad Semiconductor Inc., the industry’s leading supplier of configurable mixed-signal ASICs, has selected the company’s Analog FastSPICE (AFS) Platform for block-level characterization and full-circuit verification of their analog and mixed-signal designs.
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Jan 17, 2012
MONROVIA, California and MEYLAN, France – January 10, 2012 – Microdul AG – a specialist for high quality semiconductors and micro-systems assembly – has adopted an integrated mixed-signal flow from Dolphin Integration and Tanner EDA.
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Jan 12, 2012
SAN JOSE, California – January 11, 2012 - Real Intent, Inc., the leading provider of software products that accelerate Early Functional Verification and Advanced Sign-Off of electronic designs, announced it is now shipping Meridian™ Clock Domain Crossing (CDC) verification software Version 4.0.
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Dec 16, 2011
SANTA CLARA, CA, — December 16, 2011— Berkeley Design Automation, Inc., provider of the world’s fastest nanometer circuit verification, today announced that it has been selected as a winner of the ISA Technovation Award (Dec 2011) in the Semiconductor (Intellectual Property) category by the India Semiconductor Association (ISA).
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Dec 15, 2011
MOUNTAIN VIEW, Calif. – December 14, 2011- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced that IC Compiler-Advanced Geometry (AG) drove silicon success for GLOBALFOUNDRIES’ first major 20-nanometer (nm) chip. Recently announced, IC Compiler-AG is the 20-nm edition of IC Compiler. The tapeout of this large design containing a dual-core processor represents a major milestone in the collaboration between Synopsys and GLOBALFOUNDRIES to develop 20-nm rules and a comprehensive double patterning technology (DPT)-aware implementation solution. The selection of IC Compiler for this critical design further strengthens IC Compiler’s technological leadership in 20-nm design. Other components of Synopsys’ Galaxy™ Implementation Platform were also used in the design, including StarRC™ extraction and PrimeTime® static timing analysis.
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Dec 15, 2011
MOUNTAIN VIEW, Calif.—December 14, 2011—Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, and Global Unichip Corporation (GUC; TW: 3443), the Flexible ASIC Leader™, today announced that GUC has achieved more than one gigahertz frequency on a dual-core ARM® Cortex™-A9 MPCore™ processor with Synopsys IC Compiler, a key component of Synopsys’ Galaxy™ Implementation Platform. Synopsys’ high-performance Galaxy implementation methodology was instrumental in achieving more than one gigahertz frequency with minimum power, while reducing schedule risk.
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Dec 14, 2011
LOUISVILLE, Colo. – December 14, 2011 -- The Design Automation Conference (DAC), the premier event on automation and design of electronic systems, features the User Track, an exciting forum for design professionals to share their work with other experts. DAC invites system designers, application engineers, IC designers, design-flow developers and vendor-customer teams to submit two-page abstracts for consideration. A typical User Track contribution describes solutions to practical issues related to EDA tools in a design flow. The User Track is part of the 49th DAC, which will be held at the Moscone Center in San Francisco, California, from June 3-7, 2012.
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Dec 13, 2011
DUBLIN, Ireland, December 13th 2011 - Duolog Technologies, the award-winning developer of IP and SoC integration products, today announced that semiconductor industry veteran and SystemC guru, Jack Donovan, has joined the Duolog team. Based in the company’s Galway, Ireland office, Donovan will focus on further expanding the capabilities of Duolog’s Socrates tool suite in the ESL and TLM domains.
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Dec 12, 2011
LOUISVILLE, Colo. – December 12, 2011 -- The Design Automation Conference (DAC), the premier event on automation and design of electronic systems, announces its first ever EDA algorithm competition. The results will be announced two weeks prior to the 49th DAC, which will be held at the Moscone Center in San Francisco, California, from June 3-7, 2012. Awards will be presented at a ceremony during DAC. Prize money will be distributed among the highest performing teams.
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Dec 9, 2011
MOUNTAIN VIEW, Calif. - Dec. 8, 2011 - Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced that GLOBALFOUNDRIES has certified Synopsys’ IC Validator physical verification product for 28-nanometer (nm), 40-nm and 65-nm physical signoff, with immediate availability of design rule checks (DRC) and layout-versus-schematic (LVS) runsets to GLOBALFOUNDRIES customers. IC Validator, part of the Galaxy™ Implementation Platform, is an ideal add-on to IC Compiler for In-Design Physical Verification, making it possible for place and route engineers to accelerate time to tapeout by eliminating late-stage surprises and manual fixes. GLOBALFOUNDRIES’ qualification of IC Validator brings the unique benefits of In-Design Physical Verification to design teams working with GLOBALFOUNDRIES’ 28-nm, 40-nm and 65-nm process nodes.
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Nov 22, 2011
LOUISVILLE, COLO. –– November 22, 2011 –– The Design Automation Conference (DAC), the premier conference devoted to design and design automation of electronic systems, is soliciting industry experts and thought leaders for participation in invited sessions, panels and other events at the 49th DAC.
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Nov 16, 2011
MOUNTAIN VIEW, Calif., November 16, 2011 -- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP used in the design, verification and manufacture of electronic components and systems, today announced updates to its Identify® and Certify® FPGA-based prototyping tools. Algorithm advancements in the latest Certify software release produce up to 30 percent faster FPGA-to-FPGA transmission performance using High-Speed Time Domain Multiplexing (HSTDM), which results in higher overall performance of designs prototyped with Synopsys’ HAPS® FPGA-based prototyping systems. The new Certify and Identify software tools also incorporate incremental compilation technology that accelerates implementation of design revisions, as well as automation to ease the partitioning of large designs into multiple HAPS boards.
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Sep 30, 2011
The Design Automation Conference (DAC), the premier conference devoted to design and design automation of electronic systems (EDA), is seeking submissions that deal with tools, algorithms, EDA tool usage and design technologies for all aspects of electronic circuit, system, and embedded system and software (ESS), for DAC 2012.
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Jun 19, 2011
DAC is back, EE Times is back, the EDA forecast is up and we have made the transition to ESL design. It was a great DAC. It was almost as if the last decade hadn’t happened.
Yes we survived!
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Jun 17, 2011
Cassidy: Steve Wozniak is part Apple founder, part Mad Hatter, part Fred Astaire
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Jun 16, 2011
YES, I will be wearing my Signature White Jacket!
Every year around this time I start to hear the grumbling about DAC…No one wants to go to (fill in the City, other than San Francisco); or no one goes, it is a waste of time; or is Mark going to wear his White Sport Coat again; (OK I made that one up).
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Jun 10, 2011
Emphasis turns to embedded design
The 2011 Design Automation Conference held this week here showed a double digit increase in all attendance categories, according to the 48th DAC Executive Committee.
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Mar 29, 2011
Yes, you heard it right: Steve Wozniak will be keynoting at DAC 2011, bringing his joie de vivre and general engineering good cheer to the Electronic Design Automation community.
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Mar 25, 2011
It's never too early to get prepared for the Design Automation Conference, taking place from June 5 to 10 in San Diego, Calif. A discussion with Leon Stok, general chair of the 48th DAC, and Patrick Goreneveld, the upcoming chair for DAC 2012, outlined new initiatives to break barriers and encourage an open and constructive dialog between designers, researchers, EDA tool developers and vendors.
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