PAVILION PANEL
SOC Verification: Are We There Yet?
Topic Area:
Verification and Test
Wednesday, June 16, 2010
Time: 4:30 PM — 5:15 PM
Location:
Booth #694
Summary:
Top-down verification cannot find low-level bugs, while bottom-up methodologies cannot stitch together top-level interactions. There are many ways to approach SOC verification but all of them have tradeoffs. Which method should you use for your design? How much verification is enough? This panel will discuss verification methodologies for SOC designs and their requirements for the future.
Click here to view Pavilion Panel videos.
| Chair: | JL Gray - Verilab, Inc., Austin, TX | | Organizer: | Richard Nordin - Breker Verification Systems, Inc., Austin, TX | | | | Speakers: | John Goss - IBM Corp., Raleigh, NC | | | Rowland Reed - Qualcomm, Inc., Austin, TX | | | Dave Whipp - NVIDIA Corp., Santa Clara, CA |
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