Session: 1 | Title: PANEL: Wall Street Evaluates EDA Time: 10:30 to 12:00 | RM : Auditorium B Chair: Aart de Geus - Synopsys, Inc., Mountain View, CA Organizers: The EDA sector is capturing unprecedented attention on Wall Street. With seven IPOs in 2001 alone and strong performance by the EDA “blue chips,” the industry has gained new prominence with the capital markets. In this panel, Aart de Geus will moderate a discussion between representatives of the various constituencies who play a role in shaping Wall Street’s opinion of EDA: financial analysts, portfolio managers, venture capitalists, CEOs, and the press. Questions discussed will include: How do investors and analysts currently view EDA? What contributes to that perception? What factors drive EDA’s current favor with Wall Street, and why is the sector “hot” compared to two to three years ago? How do we sustain that favor? Given the highly complex nature of our industry, how do investors decipher the strength of a particular EDA firm? Is EDA tied to the semiconductor industry’s performance? What role does the press play in shaping the view? 1.1 Wall Street Evaluates EDA Speaker: Moshe Gavrielov, - Verisity Design, Inc.Richard Goering, - EE TimesLucio Lanza, - Lanza Tech. VenturesJay Vleeschhouwer, - Merrill Lynch Tech. ResearchVishal Saluja, - J. & W. Seligman & Co. Inc. Authors: ********************************************************************************** Session: 2 | Title: Web and IP Based Design Time: 10:30 to 12:00 | RM : 292 Chair: Gang Qu - Univ. of Maryland, College Park, MD Organizers: Ahmed A Jerraya, Krzysztof Kuchcinski Web created new opportunities for geographically distributed design process but at the same time it introduced a number of challenges. The first paper presents techniques for IP delivery using Java applets. The second paper proposes generic techniques for watermarking-based IP protection that is essentially applicable to an arbitrary optimization and design problem. The third paper enables simulation of a design in the web environment. The final paper makes design process more flexible by leveraging on engineering change methodology. 2.1 IP Delivery for FPGAs Using Applets and JHDL Speaker: Michael J. Wirthlin, - Brigham Young Univ. Authors:Michael J. Wirthlin, , Brian McMurtrey- Brigham Young Univ., Provo, Utah 2.2 Watermarking Integer Linear Programming Solutions Speaker: Seapahn Megerian, - Univ. of California Authors:Seapahn Megerian, Milenko Drinic, , Miodrag Potkonjak- Univ. of California, Los Angeles, CA 2.3s Model Design using Hierarchical Web-based Libraries Speaker: Fabrice Bernardi, - Univ. of Corsica Authors:Fabrice Bernardi, , Jean F. Santucci- Univ. of Corsica, Corte, France 2.4s Behavioral Synthesis via Engineering Change Speaker: Milenko Drinic, - Univ. of California Authors:Milenko Drinic - Univ. of California, Los Angeles, CA, , Darko Kirovski- Microsoft Research, Redmond, WA ********************************************************************************** Session: 3 | Title: Design Innovations for Embedded Processors Time: 10:30 to 12:00 | RM : 288 Chair: Vojin Zivojnovic - Axys Design Automation, Inc., Irvine, CA Organizers: Grant E Martin, Majid Sarrafzadeh This session presents a number of interesting innovations in design techniques for embedded processors. The first paper reveals a novel technique for mixing compiled-code and interpreted-code approaches to instruction-set simulation. The second paper introduces the idea of incorporating optimized hardware for profiling memory. The final paper reduces instruction memory size using decompression hardware. 3.1 A Universal Technique for Fast and Flexible Instruction-Set Architecture Simulation Speaker: Achim Nohl, - LISATek Inc. Authors:Achim Nohl - LISATek Inc., Menlo Park, CA, , Gunnar Braun- Aachen Univ. of Tech., Aachen, Germany, , Andreas Hoffmann- LISATek Inc., Menlo Park, CAOliver Schliebusch, Heinrich Meyr, Rainer Leupers, - Aachen Univ. of Tech., Aachen, Germany 3.2 A Fast On-Chip Profiler Memory Speaker: Roman Lysecky, - Univ. of California Authors:Roman Lysecky, Susan Cotterell, , Frank Vahid- Univ. of California, Riverside, CA 3.3 Design of an One-Cycle Decompression Hardware for Performance Increase in Embedded Systems Speaker: Haris Lekatsas, - NEC Authors:Haris Lekatsas, Joerg Henkel, , Venkata Jakkula- NEC, Princeton, NJ ********************************************************************************** Session: 4 | Title: Passive Model Order Reduction Time: 10:30 to 12:00 | RM : 287 Chair: Jacob K. White - Massachusetts Institute of Tech., Cambridge, MA Organizers: Jaijeet Roychowdhury, Mustafa Celik Three excellent papers are presented in this session, with the theme of rigorous approaches to linear passive MOR addressing important theoretical and practical issues.The first paper presents a framework for MOR based on generalized factors that includes popular methods like PRIMA as special cases. The second paper presents a convincing argument that causality is key to effective passive MOR of distributed systems. The final demonstrates that attentiveness to positive real properties ensures passivity in truncated balanced realizations. 4.1 A Factorization-Based Framework for Passivity-Preserving Model Reduction of RLC Systems Speaker: Qing Su, - Purdue Univ. Authors:Qing Su, Venkataramanan Balakrishnan, , Cheng-Kok Koh- Purdue Univ., West Lafayette, IN 4.2 Model Order Reduction for Strictly Passive and Causal Distributed Systems Speaker: Luca Daniel, - Univ. of California Authors:Luca Daniel - Univ. of California, Berkeley, CA, , Joel R. Phillips- Cadence Design Systems, Inc., San Jose, CA 4.3 Guaranteed Passive Balancing Transformations for Model Order Reduction Speaker: Joel R. Phillips, - Cadence Berkeley Labs. Authors:Joel R. Phillips - Cadence Berkeley Labs., San Jose, CA, , Luca Daniel- Univ. of California, Berkeley, CA, , Miguel Silveira- INESC, Lisboa, Portugal ********************************************************************************** Session: 5 | Title: New Perspectives in Physical Design Time: 10:30 to 12:00 | RM : Auditorium A Chair: Steven Teig - Simplex Solutions, Inc., Sunnyvale, CA Organizers: Ralph Otten, Timothy Kam This session presents early, innovative examples of what promise to be some of the next trends in physical design. 5.1 Uncertainty-Aware Circuit Optimization Speaker: Xiaoliang Bai, - Univ. of California at San Diego Authors:Xiaoliang Bai - Univ. of California at San Diego, La Jolla, CA, Chandu Visweswariah, Philip N. Strenski, , David J. Hathaway, - IBM Corp., Essex Junction, VT 5.2 Congestion-Driven Codesign of Power and Signal Networks Speaker: Haihua Su, - IBM Corp. Authors:Haihua Su, , Jiang Hu- IBM Corp., Austin, TX, , Sachin S. Sapatnekar- Univ. of Minnesota, Minneapolis, MN, Sani R. Nassif, - IBM Corp., Austin, TX 5.3 On Metrics for Comparing Routability Estimation Methods for FPGAs Speaker: Parivallal Kannan, - Univ. of Texas Authors:Parivallal Kannan, Shankar Balachandaran, , Dinesh Bhatia- Univ. of Texas, Dallas, TX ********************************************************************************** Session: 6 | Title: PANEL: Tools or Users: Which is the Bigger Bottleneck? Time: 2:00 to 4:00 | RM : Auditorium B Chair: Andrew B. Kahng - Univ. of California at San Diego, La Jolla, CA Organizers: As chip design becomes ever more complex, fewer design teams are succeeding. Who's to blame? On one hand, tools are hard to use, buggy, not interoperable, and have missing functionality. On the other hand, there is a wide range of engineering skills, and tools can be abused within flawed methodologies. This panel will quantify and prioritize the key gaps that must be addressedon both sides. 6.1 Tools or Users: Which is the Bigger Bottleneck? Speaker: Nancy Nettleton, - Sun MicrosystemsLambert Van den Hoven, - PhilipsLavi Lev, - Cadence Design Systems, Inc.Patrick Groeneveld, - Magma Design Automation, Inc.Paul Rodman, - ReShape, Inc. Authors: ********************************************************************************** Session: 7 | Title: SPECIAL SESSION: Life After CMOS: Imminent or Irrelevant? Time: 2:00 to 4:00 | RM : Auditorium A Chair: Dennis Sylvester - Univ. of Michigan, Ann Arbor, MI Organizers: With the introduction of 90nm CMOS processes as early as the fourth quarter of this year, we are finally entering the heralded nanometer CMOS regime. In nanoscale CMOS, many fundamental questions now become more pressing: how far can we scale the traditional planar CMOS paradigm, what device technologies are in development that can potentially replace CMOS and when? This session addresses both evolutionary and revolutionary approaches to continuing along Moore's Law. We start with industrial perspectives on how to best extend the lifespan of CMOS as we know it with the latter half of the session devoted to more radical departures from today's devices. 7.1 Life is CMOS: Why Chase the "Life-after"? Speaker: George Sery, - Intel Corp. Authors:George Sery, Shekhar Borkar, , Vivek De- Intel Corp., Hillsboro, OR 7.2 The Next Chip Challenge: Effective Methods for Viable Mixed Technology SoCs Speaker: H. Bernhard Pogge, - IBM Microelectronics Authors:H. Bernhard Pogge - IBM Microelectronics, Hopewell Junction, NY 7.3 Few Electron Devices: Towards Hybrid CMOS-SET Integrated Circuits Speaker: Adrian Ionescu, - Swiss Federal Institute of Tech. Authors:Adrian Ionescu, Michel J. Declercq, , Santanu Mahapatra- Swiss Federal Institute of Tech., Lausanne, Switzerland, Kaustav Banerjee, - Stanford Univ., Stanford, CA, , Jacques Gautier, - CEA-DRT - LETI/DTS, Grenoble, France 7.4 Carbon Nanotube Field-Effect Transistors for Logic Applications Speaker: Richard Martel, - IBM Corp. Authors:Richard Martel, V. Derycke, J. Appenzeller, S. Wind, , Ph. Avouris, - IBM Corp., Yorktown Heights, NY ********************************************************************************** Session: 8 | Title: Formal Verification Time: 2:00 to 4:00 | RM : 292 Chair: Yaron Wolfsthal - IBM Corp., Haifa, ISR Organizers: Carl Pixley, Karem Sakallah The need and benefits of formal verification (FV) have been accepted for some time. The capacity of FV-based tools is still limited and in this session new technologies and methodologies are presented that enable larger designs to be formally verified. In particular, novel ideas to enhance symbolic simulation, hybrid approach that uses symbolic simulation and model checking and SAT and BDD bounded model-checking. 8.1 Efficient State Representation for Symbolic Simulation Speaker: Valeria Bertacco, - Stanford Univ. Authors:Valeria Bertacco, , Kunle Olukotun- Stanford Univ., Stanford, CA 8.2 Handling Special Constructs in Symbolic Simulation Speaker: Alfred Koelbl, - Tech. Univ. of Munich Authors:Alfred Koelbl - Tech. Univ. of Munich, Munich, Germany, , James Kukula- Synopsys, Inc., Beaverton, OR, , Kurt Antreich- Tech. Univ. of Munich, Munich, Germany, Robert Damiano, - Synopsys, Inc., Beaverton, OR 8.3 A Hybrid Verification Approach: Getting Deep into the Design Speaker: Gila Kamhi, - Intel Corp. Authors:Scott Hazelhurst - Univ. of the Witwatersrand, Johannesburg, S. Africa, Osnat Weissberg, Gila Kamhi, , Limor Fix, - Intel Corp., Haifa, Israel 8.4 Can BDDs Compete with SAT Solvers on Bounded Model Checking? Speaker: Gianpiero Cabodi, - Politecnico di Torino Authors:Gianpiero Cabodi, Paolo E. Camurati, , Stefano Quer- Politecnico di Torino, Turin, Italy ********************************************************************************** Session: 9 | Title: High Level Specification and Design Time: 2:00 to 4:00 | RM : 288 Chair: Andreas Kanstein - Motorola, Inc., Austin, TX Organizers: Limor Fix, Shin-ichi Minato With increasing design complexity, different technologies have been developed to bridge the gap between the amount of logic that can be put on a chip and the design and verification effort necessary to build such a chip. In the session, C-based design methodology is presented. High level specification is used for generation of IP monitors, for designing pipeline control and for constraining the design envionment. 9.1 RTL C-Based Methodology for Designing and Verifying a Multi-Threaded Processor Speaker: Luc Semeria, - Synopsys, inc. Authors:Luc Semeria - Synopsys, Inc., Mountain View, CA, , Andrew Seawright- 0-In Design Automation, Inc., San Jose, CA, , Renu Mehra- Synopsys, Inc., Mountain View, CA, Daniel Ng, - Broadcom, Inc., San Jose, CA, , Arjuna Ekanayake, , CA, , Barry Pangrle, - Synopsys, Inc., Mountain View, CA 9.2 High-Level Specification and Automatic Generation of IP Interface Monitors Speaker: Marcio T. Oliveira, - Univ. of British Columbia Authors:Marcio T. Oliveira, , Alan J. Hu- Univ. of British Columbia, Vancouver, BC 9.3 Achieving Maximum Performance: A Method for the Verification of Interlocked Pipeline Control Logic Speaker: Kerstin I. Eder, - Univ. of Bristol Authors:Kerstin I. Eder - Univ. of Bristol, Bristol, Great Britain, , Geoff Barrett- Broadcom Corp., Bristol, Great Britain 9.4 Formal Verification of Module Interfaces Against Real Time Specifications Speaker: Pallab Dasgupta, - Indian Institute of Tech. Authors:Arindam Chakrabarti - Univ. of California, Berkeley, CA, Pallab Dasgupta, Partha P. Chakrabarti, , Ansuman Banerjee, - Indian Institute of Tech., Kharagpur, India ********************************************************************************** Session: 10 | Title: Timing Abstraction Time: 2:00 to 4:00 | RM : 287 Chair: Mark Hahn - Cadence Design Systems, Inc., San Jose, CA Organizers: Chandu Visweswariah, Narendra V Shenoy Hierarchical timing verification and re-use of IP blocks require accurate timing abstraction. The first three papers of this session present various approaches to efficient generation of timing abstractions. The last paper applies ATPG and implication techniques to automatically detect multi-cycle paths in sequential circuits. 10.1 Automated Timing Model Generation Speaker: Loa Mize, - Synopsys, Inc. Authors:Ajay J. Daga, Loa Mize, Subramanyam Sripada, Chris Wolff, , Qiuyang Wu, - Synopsys, Inc., Hillsboro, OR 10.2 Timing Model Extraction of Hierarchical Blocks by Graph Reduction Speaker: Cho Moon, - Cadence Design Systems, Inc. Authors:Cho Moon, Harish Kriplani, , Krishna P. Belkhale- Cadence Design Systems, Inc., San Jose, CA 10.3 Efficient Stimulus Independent Timing Abstraction Model Based on a New Concept of Circuit Block Transparency Speaker: Martin Foltin, - Hewlett-Packard Authors:Martin Foltin, Brian Foutz, , Sean C. Tyler- Hewlett-Packard, Fort Collins, CO 10.4 An Implication-based Method to Detect Multi-Cycle Paths in Large Sequential Circuits Speaker: Hiroyuki Higuchi, - Fujitsu Labs. Ltd. Authors:Hiroyuki Higuchi - Fujitsu Labs. Ltd., Kawasaki, Japan ********************************************************************************** Session: 11 | Title: SPECIAL SESSION: E-Textiles Time: 4:30 to 6:00 | RM : Auditorium B Chair: Majid Sarrafzadeh - Univ. of California, Los Angeles, CA Organizers: Majid Sarrafzadeh Topics: Enabling technologies and fabrication techniques for the economical manufacture of large-area, flexible, conformable e-textiles applications. E-textiles represents a revp;itopmaru step by bringing together textiles and electronics in a common effort to integrate many elementary sensors, actuators, logic, and power sources sparsely distributed application, with highly unreliable behavior, but with stringent constraints on opertional longevity. On-th-fly reconfigurability and adaptability with low computational overhead. Device and technology challenges imposed by embedding simple computational elements into fabric, by building yarns with computational capabilities, or by the need of unconventional power sources. 11.1 Reconfigurable Fabric Speaker: Glenn Reinmann, - Univ. of California Authors:Glenn Reinmann, Deborah Estrin, Mani Srivatsava, , Majid Sarrafzadeh, - Univ. of California, Los Angeles, CA 11.2 The Wearable Motherboard: A Framework for Personalized Mobile Information Processing (PMIP) Speaker: Sundaresan Jayaraman, - Georgia Institute of Tech. Authors:Sungmee Park, , Sundaresan Jayaraman- Georgia Institute of Tech., Atlanta, GA, , Ken Mackenzie- Gerogia Institute of Tech., Atlanta, GA 11.3 Opportunities and Challenges in E-textile Modeling, Analysis and Optimization Speaker: Diana Marculescu, - Carnegie Mellon Univ. Authors:Diana Marculescu, Radu Marculescu, , Pradeep Khosla- Carnegie Mellon Univ., Pittsburgh, PA ********************************************************************************** Session: 12 | Title: PANEL: Analog Intellectual Property: Now? or Never? Time: 4:30 to 6:00 | RM : Auditorium A Chair: Stephen Ohr - EET/CMP Media, San Francisco, CA Organizers: With more and more Systems-on-chip makers hoping to include analog functional blocks as a means of differentiating their designs, it is therefore tempting to believe that analog intellectual properties (IP) can be created, traded and integrated with the same tools and methodologies with which digital IP are moved about. But is analog IP a viable business? Can analog IPs be traded — given that design tuning is needed for every new chip variant, and every new process generation? Certainly, silicon foundries need to rely on a wide set of external IP offerings, in order to allow their users to build complete systems. Are they seeing enough activity in Analog IP designs to justify specialized fab runs, or the kind of process tuning that would allow analog and digital IPs to coexist on the same chip? What is the future of analog designs at the very low voltage-swings coming with sub-100nm CMOS? What CAD tools are needed to help analog designers? Are newly emerging EDA technologies, designed to enhance analog design productivity, maturing rapidly enough to be accepted by designers? Certainly many Analog IP providers and Analog EDA tool vendors would argue that the answer is yes. However, how many 'traditional' analog designers would admit they are still using kit parts and breadboards — maybe Spice and manual IC layout techniques — today in their every-day job? This panel of experts — representing analog designers, analog EDA tool providers, silicon foundries and analog IP vendors — will address these issues, and provide a likely context for analog IP development and trade. 12.1 Analog Intellectual Property: Now? or Never? Speaker: Roy McGuffin, - Antrim Design Systems, Inc.Felicia James, - Cadence Design Systems, Inc.Rudolf Koch, - Infineon Technologies AGMasao Hotta, - Hitachi Ltd.Mike Brunolli, - Nurlogic Design, Inc. Authors: ********************************************************************************** Session: 13 | Title: Low-Power System Design Time: 4:30 to 6:00 | RM : 292 Chair: Giovanni De Micheli - Stanford Univ., Stanford, CA Organizers: Renu Mehra, Enrico Macii This session deals with system level power minimization using dynamic voltage scaling. The first paper describes task scheduling algorithms that minimize energy in a multiprocessor environment. The second paper describes task scheduling algorithms that maximize battery life. The third paper minimizes energy in a multiprocessor environment by allowing each loop nest to be executed with multiple process and shutting off unused processors. 13.1 Task Scheduling and Voltage Selection for Energy Minimization Speaker: Yumin Zhang, - Synopsys, Inc. Authors:Yumin Zhang - Synopsys, Inc., Mountain View, CA, Xiaobo Sharon Hu, , Danny Z. Chen- Univ. of Notre Dame, Notre Dame, IN 13.2 Battery-Conscious Task Sequencing for Portable Devices Including Voltage/Clock Scaling Speaker: Daler Rakhmatov, - Univ. of Arizona Authors:Daler Rakhmatov, , Sarma Vrudhula- Univ. of Arizona, Tucson, AZ, , Chaitali Chakrabarti- Arizona State Univ., Tempe, AZ 13.3 An Energy Saving Strategy Based on Adaptive Loop Parallelization Speaker: Ismail Kadayif, - Penn State Univ. Authors:Ismail Kadayif, , Mahmut T. Kandemir- Penn State Univ., University Park, PA, , Mustafa Karakoy- Imperial College, London, Great Britain ********************************************************************************** Session: 14 | Title: Fabric-Driven Logic Synthesis Time: 4:30 to 6:00 | RM : 288 Chair: Tiziano Villa - Parades, Roma, ITA Organizers: Malgorzata Marek-Sadowska, Steven Nowick Papers in this section discuss synthesis approaches which target specific fabrics. The first paper proposes a new regular layout structure and discusses logic synthesis for it. The second paper describes a modified Bellman-Ford algorithm for cycle stealing in FPGAs. The third paper shows how layout information can improve carry-save adder designs. 14.1 River PLAs: A Regular Circuit Structure Speaker: Fan Mo, - Univ. of California Authors:Fan Mo, , Robert K. Brayton- Univ. of California, Berkeley, CA 14.2 Cycle Stealing Boosts FPGA Performance Speaker: John P. Fishburn, - Agere Systems, Inc. Authors:William B. Andrews, Barry K. Britton, , Xiaotao Chen- Lattice Semiconductor, Inc., Allentown, PA, Alfred E. Dunlop, - Consultant, Murray Hill, NJ, , John P. Fishburn, - Agere Systems, Inc., Murray Hill, NJ, , Harold N. Scholz, - Lattice Semiconductor, Inc., Allentown, PA 14.3 Layout-Aware Synthesis of Arithmetic Circuits Speaker: Junhyung Um, - KAIST Authors:Junhyung Um, , Taewhan Kim- KAIST, Taejon, Korea ********************************************************************************** Session: 15 | Title: Memory Management and Address Optimization in Embedded Systems Time: 4:30 to 6:00 | RM : 287 Chair: Nikil Dutt - Univ. of California, Irvine, CA Organizers: Diederik Verkest, Luca Benini Memory access and addressing is often a critical issue in embedded system design. The papers in this session describe approaches to reduce/eliminate memory bottlenecks. 15.1 Automatic Data Migration for Reducing Energy Consumption in Multi-Bank Memory Systems Speaker: Victor M. De La Luz, - Penn State Univ. Authors:Victor M. De La Luz, , Mahmut T. Kandemir- Penn State Univ., University Park, PA, , Ibrahim Kolev- UMIST, Manchester, United Kingdom 15.2 Exploiting Shared Scratch Pad Memory Space in Embedded Multiprocessor Systems Speaker: J. Ramanujam, - Louisiana State Univ. Authors:Mahmut T. Kandemir - Penn State Univ., University Park, PA, , J. Ramanujam- Louisiana State Univ., Baton Rouge, LA, , Alok Choudhary- Northwestern Univ., Evanston, IL 15.3 Address Assignment Combined with Scheduling in DSP Code Generation Speaker: Yoonseo Choi, - KAIST Authors:Yoonseo Choi, , Taewhan Kim- KAIST, Taejon, Korea ********************************************************************************** Session: 16 | Title: SPECIAL SESSION: Optics: Lighting the Way to EDA Riches? Time: 8:30 to 10:00 | RM : Auditorium B Chair: Jaijeet Roychowdhury - Univ. of Minnesota, Minneapolis, MN Organizers: Jaijeet Roychowdhury, Joel R Phillips Optical communication has been a key enabler in the development of the Internet. Now it is being considered for on-chip signalling and communication as well. What implications does optics hold for the future of chip design and of EDA? Have EDA and optical CAD anything in common? Can they benefit each other? We look into these questions in this special session, consisting of two invited lectures and a contributed paper. The first talk is an overview of optical systems and their use in communications. The second focuses on computer-aided design techniques in optical communications. The final presentation describes a fast technique for computing optical fields propagating in free space. 16.1 The Optical Internet and the Drive Towards Multifunctional Hybrid Optoelectronic Integration Speaker: Edward H. Sargent, - Univ. of Toronto Authors:Edward H. Sargent - Univ. of Toronto, Toronto, ON, Canada 16.2 Computer Aided Design of Long-Haul Optical Fiber Transmission Systems Speaker: J. F. Maloney, - PhotonEx Corp. Authors:J. F. Maloney - PhotonEx Corp., Maynard, MA, , C. R. Menyuk- Univ. of Maryland, Baltimore, MD 16.3 A Fast Optical Propagation Technique for Modeling Micro-Optical Systems Speaker: Timothy P. Kurzweg, - Univ. of Pittsburgh Authors:Timothy P. Kurzweg, Steven P. Levitan, Jose A. Martinez, Mark Kahrs, , Donald M. Chiarulli, - Univ. of Pittsburgh, Pittsburgh, PA ********************************************************************************** Session: 17 | Title: PANEL: Nanometer Design: What Hurts Next? Time: 8:30 to 10:00 | RM : Auditorium A Chair: Lawrence T. Pileggi - Carnegie Mellon Univ., Pittsburgh, PA Organizers: Every year, the design and EDA communities are besieged by dire warnings about the impending doom of "design as we know it". Every year, another unpleasant physical effect from the evil depths of deep submicron physics surfaces, compromising our designs in new and vile ways. Every year, the same story: more nanometer woes. Rather than endorse a new winner in this year's race for the "next worst thing" from the nanometer arena, this panel gathers a set of world-class technology experts to debate what effects are hiding just around the next corner, waiting to pounce on the unwary tool or chip designer. Which among these is really the most important, when will it happen, and why? 17.1 Nanometer Design: What Hurts Next? Speaker: Bob Brodersen, - Univ. of CaliforniaAnthony Hill, - Texas InstrumentsJohn Kibarian, - PDF SolutionsDesmond Kirkpatrick, - Intel Corp.Mark Lavin, - IBM Corp. Authors: ********************************************************************************** Session: 18 | Title: Novel DFT, BIST and Diagnosis Techniques Time: 8:30 to 10:00 | RM : 292 Chair: Rathish Jayabharathi - Intel Corp., Folsom, CA Organizers: TM Mak This session presents several novel ideas on DFT, BIST and diagnosis. The first paper discusses a DFT technique that utilizes clock control to simplify ATPG. The second paper tackles diagnosis problems with the conventional MISR signatures. The third paper presents a DFT technique to accommondate unknown output values in a BIST scheme. The last paper explores the diagnosis capability of software-based self-test. 18.1 Low-Cost Sequential ATPG with Clock-Control DFT Speaker: Miron Abramovici, - Agere Systems Authors:Miron Abramovici - Agere Systems, Murray Hill, NJ, Xiaoming Yu, , Liz Rudnick- Univ. of Illinois, Urbana, IL 18.2 Effective Diagnostics Through Interval Unloads in a BIST Environment Speaker: Peter Wohl, - Synopsys, Inc. Authors:Peter Wohl, Greg Maston, John Waicukauski, , Sanjay Patel, - Synopsys, Inc., Beaverton, OR 18.3s On Output Response Compression in the Presence of Unknown Output Values Speaker: Irith Pomeranz, - Purdue Univ. Authors:Irith Pomeranz - Purdue Univ., West Lafayette, IN, , Sandip Kundu- Intel Corp., Austin, TX, , Sudhakar M. Reddy- Univ. of Iowa, Iowa City, IA 18.4s Software-Based Diagnosis for Processors Speaker: Li Chen, - Univ. of California at San Diego Authors:Li Chen, , Sujit Dey- Univ. of California at San Diego, La Jolla, CA ********************************************************************************** Session: 19 | Title: Case Studies in Embedded System Design Time: 8:30 to 10:00 | RM : 288 Chair: Wayne Wolf - Princeton Univ., Princeton, NJ Organizers: Anand Raghunathan This session showcases case studies and experiences using application specific design methodologies in the design of embedded systems. The presentations include the design of a Viterbi decoder for wireless handsets, the use of a cost model for Hardware/Software co-design in the design of a digital camera, and the generation of efficient software for H.263 image compression. 19.1 Design of a High-Throughput Low-Power IS95 Viterbi Decoder Speaker: Xun Liu, - Univ. of Michigan Authors:Xun Liu, , Marios C. Papaefthymiou- Univ. of Michigan, Ann Arbor, MI 19.2 A Detailed Cost Model for Concurrent Use With Hardware/Software Co-Design Speaker: Peter Sandborn, - Univ. of Maryland Authors:Daniel Ragan, , Peter Sandborn- Univ. of Maryland, College Park, MD, , Paul Stoaks- Foresight-Systems, Inc., Austin, TX 19.3 Efficient Code Synthesis from Extended Dataflow Graphs for Multimedia Applications Speaker: Hyunok Oh, - Seoul National Univ. Authors:Hyunok Oh, , Soonhoi Ha- Seoul National Univ., Seoul, Korea ********************************************************************************** Session: 20 | Title: Theoretical Foundations of Embedded System Design Time: 8:30 to 10:00 | RM : 287 Chair: Rajesh Gupta - Univ. of California, Irvine, CA Organizers: Annette Reutter, Donatella Sciuto This session presents three formal approaches dealing with performance analysis and refinement transformations in embedded systems design. The first paper introduces formal transformation methods for the refinement of an abstract model into an implementation model. The second paper presents a compositional approach to analyze the timing behavior of complex systems under different scheduling strategies. The final paper shows a new timing generation method for the performance analysis of embedded software. 20.1 Transformation Based Communication and Clock Domain Refinement for System Design Speaker: Ingo Sander, - Royal Institute of Tech. Authors:Ingo Sander, , Axel Jantsch- Royal Institute of Tech., KISTA, Sweden 20.2 Model Composition for Scheduling Analysis in Platform Design Speaker: Kai R. Richter, - Tech. Univ. of Brauwnschweig Authors:Kai R. Richter - Tech. Univ. of Brauwnschweig, Braunschweig, Germany, Dirk Ziegenbein, Marek Jersak, , Rolf Ernst, - Tech. Univ. of Braunschweig, Braunschweig, Germany 20.3 Timed Compiled-Code Simulation of Embedded Software for Performance Analysis of SOC Design Speaker: Jong-Yeol Lee, - KAIST Authors:Jong-Yeol Lee, , In-Cheol Park- KAIST, Taejon, Korea ********************************************************************************** Session: 21 | Title: Equivalence Verification Time: 10:30 to 12:00 | RM : Auditorium B Chair: Ziyad Hanna - Intel Corp., Haifa, ISR Organizers: Shin-ichi Minato Using an equivalence checker to prove the functional equivalence of two designs is a common and practical verification approach. In this session, new technologies are presented that enable extraction of complex circuits, allow sequential equivalence checking and handle hard-to-verify arithmetic operators. 21.1 Automated Equivalence Checking of Switch Level Circuits Speaker: Tim McDougall, - Motorola Authors:Atanas N. Parashkevov - Motorola, Mawson Lakes, Australia, , Simon Jolly- Foursticks Pty Ltd, Frewville, Australia, , Tim McDougall- Motorola, Mawson Lakes, Australia 21.2 A Practical and Efficient Method for Compare-Point Matching Speaker: Robert Damiano, - Synopsys, Inc. Authors:Demos Anastasakis, Robert Damiano, Hi-Keung T. Ma, , Ted Stanion, - Synopsys, Inc., Hillsboro, OR 21.3 Self-Referential Verification of Gate-Level Implementations of Arithmetic Circuits Speaker: Ying Tsai Chang, - Univ. of California Authors:Ying Tsai Chang, , Kwang Ting (Tim) Cheng- Univ. of California, Santa Barbara, CA ********************************************************************************** Session: 22 | Title: PANEL: Whither (or Wither?) ASIC Handoff? Time: 10:30 to 12:00 | RM : Auditorium A Chair: Michael Santarini - EE Times, San Mateo, CA Organizers: The traditional ASIC netlist handoff is changing - but to what? Is RTL handoff finally a reality? Or, will a placement-based handoff model emerge? Are differences among underlying tool technologies and methodologies only cosmetic? Or, are there fundamental business and IP distinctions? These and other questions will be discussed as the panel examines the future of the designer - ASIC vendor relationship. 22.1 Whither (or Wither) ASIC Handoff? Speaker: Tom Russell, - IBM MicroelectronicsKazu Yamada, - NEC Corp.Tommy Eng, - Tera Systems, Inc.Sandeep Khanna, - Synopsys, Inc.Kamalesh Ruparel, - Cisco Systems, Inc. Authors: ********************************************************************************** Session: 23 | Title: Embedded Software Automation: From Specification to Binary Time: 10:30 to 12:00 | RM : 292 Chair: Joerg Henkel - NEC Research, Princeton, NJ Organizers: Marco Di Natale The increasing embedded software content of electronic systems makes it important to automate various aspects of the software design flow. This session presents papers that represent advances in embedded software automation, including synthesis from synchronous specifications, automatic library mapping for complex functions using symbolic algebra, and re-targetability of binary utilities. 23.1 Software Synthesis from Synchronous Specifications Using Logic Simulation Techniques Speaker: Yunjian Jiang, - Univ. of California Authors:Yunjian Jiang, , Robert K. Brayton- Univ. of California, Berkeley, CA 23.2 Complex Library Mapping for Embedded Software using Symbolic Algebra Speaker: Armita Peymandoust, - Stanford Univ. Authors:Armita Peymandoust - Stanford Univ., Stanford, CA, , Tajana Simunic- Hewlett-Packard Labs., Palo Alto, CA, , Giovanni De Micheli- Stanford Univ., Stanford, CA 23.3 Retargetable Binary Utilities Speaker: Jianwen Zhu, - Univ. of Toronto Authors:Maghsoud Abbaspour, , Jianwen Zhu- Univ. of Toronto, Toronto, ON, Canada ********************************************************************************** Session: 24 | Title: Applications of Reconfigurable Computing Time: 10:30 to 12:00 | RM : 288 Chair: Ivo Bolsens - Xilinx, Inc., San Jose, CA Organizers: Grant E Martin, Kurt Keutzer This session demonstrates that Reconfigurable Computing has come of age. The first paper looks at how multimedia applications will benefit through dynamic reconfiguration of operation level parallelism. The second one builds a case for partial runtime reconfiguration, demonstrated on a networking application. The final paper is a case study in which what might normally be a software testbench for disk drive design is instead built as reconfigurable hardware, giving much higher performance. 24.1 Exploiting Operation Level Parallelism through Dynamically Reconfigurable Datapaths Speaker: Zhining Huang, - Princeton Univ. Authors:Zhining Huang, , Sharad Malik- Princeton Univ., Princeton, NJ 24.2 Dynamic Hardware Plugins for FPGAs with Partial Run-Time Reconfiguration Speaker: John W. Lockwood, - Washington Univ. Authors:Edson L. Horta - LSI-EPUSP-USP, Sao Paulo, Brazil, , John W. Lockwood- Washington Univ., Saint Louis, MO, , Dave Parlour- Xilinx Inc., San Jose, CA, David Taylor, - Washington Univ., Saint Louis, MO 24.3 A Reconfigurable FPGA-Based Readback Signal Generator For Hard-Drive Read Channel Simulator Speaker: Kia Bazargan, - Univ. of Minnesota Authors:Jinghuan Chen, Jaekyun Moon, , Kia Bazargan- Univ. of Minnesota, Minneapolis, MN ********************************************************************************** Session: 25 | Title: New Test Methods Targeting Non-Classical Faults Time: 10:30 to 12:00 | RM : 287 Chair: Rob Aitken - Agilent Technologies, Santa Clara, CA Organizers: Miron Abramovici, TM Mak Complexity of VLSI testing requires targeting new type of faults in addition to the classical stuck-at fault model. The session illustrates different aspects of this struggle. 25.1 Embedded Software-Based Self-Testing for SoC Design Speaker: Angela Krstic, - Univ. of California Authors:Angela Krstic, , Wei Cheng Lai- Univ. of California, Santa Barbara, CA, Li Chen, , Kwang Ting (Tim) Cheng, - Univ. of California, Santa Barbara, CA, , Sujit Dey, - Univ. of California atSan Diego, La Jolla, CA 25.2 A Novel Wavelet Transform Based Transient Current Analysis for Fault Detection and Localization Speaker: Swarup K. Bhunia, - Purdue Univ. Authors:Swarup K. Bhunia, , Kaushik Roy- Purdue Univ., West Lafayette, IN, , Jaume Segura- Balearic Islands Univ., Mallorca, Spain 25.3s Signal Integrity Fault Analysis Using Reduced-Order Modeling Speaker: Mehrdad Nourani, - Univ. of Texas Authors:Amir Attarha, , Mehrdad Nourani- Univ. of Texas, Richardson, TX 25.4s Enhancing Test Efficiency for Delay Fault Testing Using Multiple-Clocked Schemes Speaker: Li C. Wang, - Univ. of California Authors:Jing Jia Liou, Li C. Wang, , Kwang Ting (Tim) Cheng- Univ. of California, Santa Barbara, CAJennifer Dworak, , Ray Mercer, - Texas A&M Univ., College Station, CA, , Tom Williams, - Synopsys, Inc., Boulder, CO ********************************************************************************** Session: 26 | Title: SPECIAL SESSION: How Do You Design a 10M Gate ASIC? Time: 2:00 to 4:00 | RM : Auditorium B Chair: Ahmed A. Jerraya - TIMA Lab., Grenoble Cedex, FRA Organizers: Ahmed A Jerraya, Kurt Keutzer ASIC design has always been challenging but an increasing number of design groups are unsuccessful at designs in excess of 4M logic gates. A leading industry analyst states that first-silicon success is only a tenth as likely at 10M gates as at lower complexity levels. Some designers have even claimed that design above the 4M logic gate complexity is simply impossible with the current generation of design tools. Nevertheless, a number of designers are successfully approaching the 10M gate complexity level. How are they doing it? In this session designers from three segments of the integrated-circuit design industry will describe key aspects of their design methodology that enable them to achieve silicon success on high complexity designs. 26.1 Going Mobile: The Next Horizon for Multi-Million Gate Designs in the Semiconductor Industry Speaker: Christian Berthet, - STMicroelectronics Authors:Christian Berthet - STMicroelectronics, Grenoble Cedex, France 26.2 When 10M Gates Just Isn't Enough: The GPU Challenge Speaker: Chris Malachowsky, - NVIDIA Authors:Chris Malachowsky - NVIDIA, Santa Clara, CA 26.3 Challenges in achieving First-Silicon Success for 10M-Gate SoCs: A Silicon Engineering Perspective Speaker: Aurangzeb Khan, - Simplex Solutions, Inc. Authors:Aurangzeb Khan - Simplex Solutions, Inc., Sunnyvale, CA 26.4 Panel Discussion: Is 10M Gate ASIC Design Really as Easy as They Say? Speaker: Authors:Christian Berthet - STMicroelectronics, Grenoble Cedex, France, , Andrew B Kahng- Univ. of California at San Diego, LaJolla, CA, , Arangzeb Khan- Simplex Solutions, Inc., Sunnyvale, CA, Kurt Keutzer, - Univ. of California, Berkeley, CA, , Chris Malachowsky, - NIVIDEA, Santa Clara, CA, , Ron Wilson, - ISD Magazine, San Mateo, CA ********************************************************************************** Session: 27 | Title: Power Distribution Issues Time: 2:00 to 4:00 | RM : Auditorium A Chair: Sachin Sapatnekar - Univ of Minnesota, Minneapolis, MN Organizers: Abhijit Dharchoudhury, Tadahiro Kuroda Power distribution issues are becoming extremely important as levels of integration increase. The first paper describes a model-order reduction method for hierarchical power grid analysis. The second paper describes a frequency-domain macromodel for block current signatures. The third paper describes circuit models for the chip interface, and the fourth paper describes a method for analyzing symmetrical P/G networks. The final paper describes a method to optimize clock distribution networks using supply current folding. 27.1 HiPRIME: Hierarchical and Passivity Reserved Interconnect Macromodeling Engine for RLKC Power Delivery Speaker: Yahong Cao, - Univ. of Wisconsin Authors:Yahong Cao, YuMin Lee, Tsunghao Chen, , ChungPing Chen, - Univ. of Wisconsin, Madison, WI 27.2 High-Level Current Macro-Model For Power-Grid Analysis Speaker: Srinivas Bodapati, - Univ. of Illinois Authors:Srinivas Bodapati - Univ. of Illinois, Urbana, IL, , Farid N. Najm- Univ. of Toronto, Toronto, ON, Canada 27.3s Macro-Modeling Concepts For The Chip Electrical Interface Speaker: Claude R. Gauthier, - Sun Microsystems Authors:Brian W. Amick, Claude R. Gauthier, , Dean Liu- Sun Microsystems, Sunnyvale, CA 27.4s Modeling and Analysis of Regular Symmetrically Structured Power/Ground Distribution Networks Speaker: Hui Zheng, - Carnegie Mellon Univ. Authors:Hui Zheng, , Lawrence T. Pileggi- Carnegie Mellon Univ., Pittsburgh, PA 27.5 Clock Tree Optimization in Synchronous CMOS Digital Circuits for Substrate Noise Reduction Using Folding of Supply Current Transients Speaker: Mustafa Badaroglu, - IMEC Authors:Mustafa Badaroglu, Kris Tiri, Stephane Donnay, , Piet Wambacq, - IMEC, Leuven, Belgium, , Ingrid Verbauwhede, - Univ. of California, Los Angeles, CA, , Georges G. Gielen, - Katholieke Univ., Leuven, Belgium, , Hugo De Man, - IMEC, Leuven, Belgium ********************************************************************************** Session: 28 | Title: Advances in Synthesis Time: 2:00 to 4:00 | RM : 292 Chair: Marek Perkowski - Portland State Univ., Portland, OR Organizers: Soha M Hassoun, Yusuke Matsunaga This section presents advances to the state-of-the-art in three non-mainstream areas which show promise for the future. The first paper presents a powerful backend optimizer for a leading asynchronous CAD tool which can be applied to large design examples (e.g. microprocessors). The second and third papers focus on the integration of asynchronous design with a commercial CAD tool flow. The fourth paper contributes a novel set of optimizing transformations for quantum Boolean circuits. The fifth paper significantly improves runtimes in SPP (sum of pseudo-products) minimization. 28.1 Resynthesis and Peephole Transformations for the Optimization of Large-Scale Asynchronous Systems Speaker: Tiberiu Chelcea, - Columbia Univ. Authors:Tiberiu Chelcea, , Steven M. Nowick- Columbia Univ., New York, NY 28.2s Design of Asynchronous Circuits by Synchronous CAD Tools Speaker: Alex Kondratyev, - Cadence Design Systems, Inc. Authors:Alex Kondratyev - Cadence Design Systems, Inc., Berkeley, CA, , Kelwin Lwin- ReShape Inc, Mountain View, CA 28.3s Implementing Asynchronous Circuits using a Conventional EDA Tool-Flow Speaker: Christos Sotiriou, - FORTH Authors:Christos Sotiriou - FORTH, Heraklion, Crete, Greece 28.4 Transformation Rules for Designing CNOT-Based Quantum Circuits Speaker: Shigeru Yamashita, - NTT Communication Science Lab. Authors:Shigeru Yamashita - NTT Communication Science Lab., Soraku-gun, Japan, Kazuo Iwama, , Yahiko Kambayashi- Kyoto Univ., Kyoto, Japan 28.5 Fast Three-Level Logic Minimization Based on Autosymmetry Speaker: Valentina Ciriani, - Univ. of Pisa Authors:Anna Bernasconi, Valentina Ciriani, Fabrizio Luccio, , Linda Pagli, - Univ. of Pisa, Pisa, Italy ********************************************************************************** Session: 29 | Title: Analog Synthesis & Design Methodology Time: 2:00 to 4:00 | RM : 288 Chair: C.- J. Richard Shi - Univ. of Washington , Seattle, WA Organizers: Joel R Phillips, Kartikeya Mayaram This session presents new developments in algorithms and methodology for synthesis and systematic design of analog and mixed-signal circuits. Two papers present progress in automatic model generation for synthesis. The third paper presents exploration methods for high-level design of delta-sigma modulators, and the final paper presents an A/D converter design case study. 29.1 An Efficient Optimization--Based Technique to Generate Posynomial Performance Models for Analog Integrated Circuits Speaker: Walter P. Daems, - Katholieke Univ. Authors:Walter P. Daems, Georges G. Gielen, , Willy M. Sansen- Katholieke Univ., Leuven, Belgium 29.2 Remembrance of Circuits Past: Macromodeling by Data Mining in Large Analog Design Spaces Speaker: Hongzhou Liu, - Carnegie Mellon Univ. Authors:Hongzhou Liu, Amit Singhee, Rob A. Rutenbar, , L. Richard Carley, - Carnegie Mellon Univ., Pittsburgh, PA 29.3 Optimal Design of Delta-Sigma ADCs by Design Space Exploration Speaker: Ovidiu Bajdechi, - Delft Univ. of Tech. Authors:Ovidiu Bajdechi - Delft Univ. of Tech., Delft, The Netherlands, , Georges G. Gielen- Katholieke Univ., Leuven, Belgium, , Johan H. Huijsing- Delft Univ. of Tech., Delft, The Netherlands 29.4 Systematic Design of a 200 Ms/s 8-bit Interpolating/Averaging A/D Converter Speaker: Jan Vandenbussche, - Katholieke Univ. Authors:Jan Vandenbussche, Koen Uyttenhove, Erik Lauwers, Michiel Steyaert, , Georges G. Gielen, - Katholieke Univ., Leuven, Belgium ********************************************************************************** Session: 30 | Title: Low-Power Physical Design Time: 2:00 to 4:00 | RM : 287 Chair: Massoud Pedram - Univ. of Southern California, Los Angeles, CA Organizers: Chaitali Chakrabarti, Sarma Vrudhula This session includes papers that address power optimization at the physcial level. The first two papers focus on interconnect power estimation and optimization. The first paper describes a fast accurate method for power estimation using hierarchical Petri nets. The second paper presents a method for power-delay optimal repeater insertion along interconnects. The last two papers deal with novel circuit architectures. The third paper describes a novel method for power reduction in the clock distribution network for domino logic. The last paper shows how a gate virtual ground can be introduced to acheive a significant reduction in the leakage power of SRAMs. 30.1 Petri Net Modeling of Gate and Interconnect Delays for Power Estimation Speaker: Ashok K. Murugavel, - Univ. of South Florida Authors:Ashok K. Murugavel, , Nagarajan Ranganathan- Univ. of South Florida, Tampa, FL 30.2 Power Estimation in Global Interconnects and its Reduction Using a Novel Repeater Optimization Methodology Speaker: Gaurav Chandra, - Stanford Univ. Authors:Pawan Kapur, Gaurav Chandra, , Krishna C. Saraswat- Stanford Univ., Stanford, CA 30.3 Low-Swing Clock Domino Logic Incorporating Dual Supply and Dual Threshold Voltages Speaker: Seong Ook Jung, - Univ. of Illinois Authors:Seong Ook Jung - Univ. of Illinois, Urbana, IL, , Kiwook Kim- Pluris Inc., Cupertino, CA, , Sung Mo Steve Kang- Univ. of California, Santa Cruz, CA 30.4 DRG-Cache: A Data Retention Gated-Ground Cache for Low Power Speaker: Amit Agarwal, - Purdue Univ. Authors:Amit Agarwal, Hai LI, , Kaushik Roy- Purdue Univ., West Lafayette, IN ********************************************************************************** Session: 31 | Title: PANEL: Unified Tools for SoC Embedded Systems: Mission Critical, Mission Impossible or Mission Irrelevant? Time: 4:30 to 6:00 | RM : Auditorium B Chair: Gary Smith - Dataquest, San Jose, CA Organizers: As designers struggle with developing application solutions consisting of complex systems-on-a-chip with a significant software component, they must deal with a diversity of tools with very different philosophies and assumptions, to help manage this task. On one hand are tools which assume a clean separation between the hardware and software parts of the design with an abstraction of the hardware available for software development. On the other hand are tools that try to handle the hardware and software parts of the design concurrently. What drives these different philosophies? Which of these is critical for emerging system designs? Which of these is viable going forward? Our panel of experts consisting of designers, embedded software tool providers, system design tool providers and an academic will answer these challenging questions. 31.1 Unified Tools for SoC Embedded Systems: Mission Critical, Mission Impossible or Mission Irrelevant? Speaker: Rick Chapman, - SuperH, Inc.John Fogelin, - Wind RiverKurt Keutzer, - Univ. of California, BerkeleyGrant Martin, - Cadence Design Systems, Inc.Brian Bailey, - Mentor Graphics Corp. Authors: ********************************************************************************** Session: 32 | Title: Multi-Voltage, Multi-Threshold Design Time: 4:30 to 6:00 | RM : Auditorium A Chair: Rajendran Panda - Motorola, Inc., Austin, TX Organizers: Renu Mehra, Sarma Vrudhula The availability of multiple supply voltages and dual threshold voltage offers new opportunities for making tradeoffs between energy consumption and performance. The first paper presents a method to optimally assign high Vt transistors to cluster of low Vt gates for reducing the leakage power. The second paper describes a practical methodology for dual Vt assignment and gate sizing. The third paper presents a novel application fo optimal use of multiple supply voltages. 32.1 Dynamic and Leakage Power Reduction in MTCMOS Circuits Using an Automated Efficient Gate Clustering Technique Speaker: Mohab H. Anis, - Univ. of Waterloo Authors:Mohab H. Anis - Univ. of Waterloo, Waterloo, ON, Canada, , Shawki M. Areibi- Univ. of Guelph, Guelph, ON, Canada, Mohamed K. Mahmoud, , Mohamed Elmasry, - Univ. of Waterloo, Waterloo, ON, Canada 32.2 Total Power Optimization By Simultaneous Dual-Vt Allocation and Device Sizing in High Performance Microprocessors Speaker: Tanay Karnik, - Intel Corp. Authors:Tanay Karnik, Yibin Ye, James Tschanz, Liqiong Wei, Steven M. BurnsVivek K. De, Shekhar Y. Borkar, , Venkatesh Govindarajulu, - Intel Corp., Austin, TX 32.3 An Optimal Voltage Synthesis Technique for a Power-Efficient Satellite Application Speaker: Dong In Kang, - USC/ISI Authors:Dong In Kang, Jinwoo Suh, , Stephen P. Crago- USC/ISI, Arlington, VA ********************************************************************************** Session: 33 | Title: Advanced Simulation Techniques Time: 4:30 to 6:00 | RM : 292 Chair: L. Miguel Silveira - INESC/IST, U. Lisbon, Lisboa, PRT Organizers: Georges G Gielen, Kartikeya Mayaram This session presents progress in simulation techniques for analog systems. First, techniques are presented for simulating optical systems and then for fractional-N frequency synthesizers. Next we feature two papers on RF simulation : one to include frequency-domain models in time-domain simulation, one demonstrating purely time-domain techniques for close-spaced carriers. The final paper presents a novel approach to noise analysis for nonlinear circuits in the frequency domain. 33.1 Fast and Accurate Behavioral Simulation of Fractional-N Frequency Synthesizers and other PLL/DLL Circuits Speaker: Michael H. Perrott, - Massachusettes Institute of Tech. Authors:Michael H. Perrott - Massachusettes Institute of Tech., Cambridge, MA 33.2 Time-Domain Steady-State Simulation of Frequency-Dependent Components using Multi-Interval Chebyshev Method Speaker: Joel R. Phillips, - Cadence Design Systems, Inc. Authors:Baolin Yang, , Joel R. Phillips- Cadence Design Systems, Inc., San Jose, CA 33.3s A Time-Domain RF Steady-State Method for Closely Spaced Tones Speaker: Jaijeet Roychowdhury, - Univ. of Minnesota Authors:Jaijeet Roychowdhury - Univ. of Minnesota, Minneapolis, MN 33.4s An Algorithm for Frequency-Domain Noise Analysis in Nonlinear Systems Speaker: Giorgio Casinovi, - Georgia Institute of Tech. Authors:Giorgio Casinovi - Georgia Institute of Tech., Atlanta, GA ********************************************************************************** Session: 34 | Title: Design Methodologies Meet Network Applications Time: 4:30 to 6:00 | RM : 288 Chair: Anand Raghunathan - NEC USA Inc., Princeton, NJ Organizers: Anand Raghunathan, Marco Di Natale Networking chips represent a challenging class of applications for EDA tools and methodologies. This session contains presentations that showcase novel design methodologies developed to address performance and power issues in network processors and switch fabrics. The first paper presents an advanced memory management methodology for high-performance network processors. The second presentation addresses power analysis of switch fabrics used in network routers, while the final presentation discusses memory optimizations for single chip switch fabrics. 34.1 System-Level Performance Optimization of the Data Queueing Memory Management in High-Speed Network Processors Speaker: Chantal Ykman, - IMEC Authors:Chantal Ykman, Jurgen Lambrecht, Diederik Verkest, , Francky Catthoor, - IMEC, Heverlee, Belgium, , Aris Nikologiannis, - Ellemedia, Athens, Greece, , George Konstantoulakis, - Inaccess Networks, Athens, Greece 34.2 Analysis of Power Consumption on Switch Fabrics in Network Routers Speaker: Terry Tao Ye, - Stanford Univ. Authors:Terry Tao Ye - Stanford Univ., Stanford, CA, , Luca Benini- Univ. ` di Bologna - DEIS, Bologna, Italy, , Giovanni De Micheli- Stanford Univ., Stanford, CA 34.3 Memory Optimization in Single Chip Network Switch Fabrics Speaker: David J. Whelihan, - Carnegie Mellon Univ. Authors:David J. Whelihan, , Herman Schmit- Carnegie Mellon Univ., Pittsburgh, PA ********************************************************************************** Session: 35 | Title: Advances in Analog Modeling Time: 4:30 to 6:00 | RM : 287 Chair: Alan Mantooth - Univ. of Arkansas, Fayetteville, AR Organizers: Joel R Phillips, Kartikeya Mayaram This session features topics related to modeling of analog systems. The first paper presents a high-level behavioral model for coupled oscillators. The next paper seeks to apply formal methods to analog verification problems. The third paper discusses a technique for analyzing unsolvable systems that are possible to construct in the VHDL-AMS language. The final paper presents novel quadrature schemes for computing inductance in the presence of magnetically permeable materials. 35.1 Behavioral Modeling of (Coupled) Harmonic Oscillators Speaker: Piet Vanassche, - Katholieke Univ. Authors:Piet Vanassche, Georges G. Gielen, , Willy M. Sansen- Katholieke Univ., Leuven, Belgium 35.2 Model Checking Algorithms for Analog Verification Speaker: Walter Hartong, - Univ. of Hannover Authors:Walter Hartong, Lars Hedrich, , Erich Barke- Univ. of Hannover, Hannover, Germany 35.3s Regularization of Hierarchical VHDL-AMS Models using Bipartite Graphs Speaker: Jochen Mades, - Infineon Tech. Authors:Jochen Mades - Infineon Tech., Munich, Germany, , Manfred Glesner- Darmstadt Univ. of Tech., Darmstadt, Germany 35.4s Improving the Generality of the Fictitious Magnetic Charge Approach to Computing Inductances in the Presence of Permeable Materials Speaker: Yehia M. Massoud, - Synopsys, Inc. Authors:Yehia M. Massoud - Synopsys, Inc., Mountain View, CA, , Jacob K. White- Massachusetts Institute of Tech., Cambridge, MA ********************************************************************************** Session: 36 | Title: Advances in Timing and Simulation Time: 8:30 to 10:00 | RM : Auditorium B Chair: David J. Hathaway - IBM Corp., Essex Junction, VT Organizers: Louis Scheffer, Narendra V Shenoy This session addresses extensions to static timing to take into account statistical manufacturing variations, false paths and both! In addition to timing verification, the final paper focuses on inexpensive acceleration of functional verification by using FPGAs and a special compiler. 36.1 A General Probabilistic Framework for Worst Case Timing Analysis Speaker: Michael Orshansky, - Univ. of California Authors:Michael Orshansky, , Kurt Keutzer- Univ. of California, Berkeley, CA 36.2s False Timing Path Identification using ATPG Technique and Delay-Based Information Speaker: Jing Zeng, - Motorola Authors:Jing Zeng, , Magdy Abadir- Motorola, Austin, TX, , Jacob Abraham- Univ. of Texas, Austin, TX 36.3s False-Path-Aware Statistical Timing Analysis and Efficient Path Selection for Delay Testing and Timing Validation Speaker: Jing Jia Liou, - Univ. of California Authors:Jing Jia Liou, Angela Krstic, Li C Wang, , Kwang Ting (Tim) Cheng, - Univ. of California, Santa Barbara, CA 36.4 A Fast, Inexpensive and Scalable Hardware Acceleration Technique for Functional Simulation Speaker: Srihari Cadambi, - NEC Authors:Srihari Cadambi - NEC, Princeton, NJ, Chandra S. Mulpuri, , Pranav N. Ashar- NEC, Princeton, NJ ********************************************************************************** Session: 37 | Title: PANEL: Formal Verification Methods: Getting Around the Brick Wall Time: 8:30 to 10:00 | RM : Auditorium A Chair: David L. Dill - Stanford Univ., Stanford, CA Organizers: Formal verification is moving beyond equivalence checking, a world of mathematical models and proofs. As the technology makes transition from “research” to “development”, how will designers utilize and benefit from this technology? Pessimists will attempt to bring the technology to the design environment; the optimists want to give them new tools of the trade. Which one will it be? Is the current design environment rich enough to encompass formal verification methods? Can one truly specify a design? Is a new language or framework needed to exploit the new capabilities? How much more do we need to learn to utilize these new capabilities? When will our core engines run out of steam? Our panel of experts consisting of users, tool providers, core engine builders will answer these challenging questions. 37.1 Formal Verification Methods: Getting Around the Brick Wall Speaker: Gerard Berry, - Esterel TechnologiesGunnar Stalmarck, - Prover TechnologyHarry Foster, - Verplex Systems, Inc.Limor Fix, - Intel Corp.Rajeev Ranjan, - Real Intent, Inc. Authors: ********************************************************************************** Session: 38 | Title: Routing and Buffering Time: 8:30 to 10:00 | RM : 292 Chair: Noel Menezes - Inte Corp., Hillsboro, OR Organizers: Charles J Alpert, Steven Teig Buffering is a key aspect of interconnect design. It is crucial to meld routing and timing into a consistent framework for timing closure. This session covers a range interconnect performance issues such as efficient interconnect synthesis, buffer planning with pin assignment, and implementation issues in global routing data structures. 38.1 S-Tree: A Technique for Buffered Routing Tree Synthesis Speaker: Milos Hrkic, - Univ. of Illinois Authors:Milos Hrkic, , John Lillis- Univ. of Illinois, Chicago, IL 38.2 An Algorithm for Integrated Pin Assignment and Buffer Planning Speaker: Hua Xiang, - Univ. of Texas Authors:Hua Xiang, Xiaoping Tang, , D. F. Wong- Univ. of Texas, Austin, TX 38.3 An Efficient Routing Database Speaker: Narendra V. Shenoy, - Synopsys, Inc. Authors:Narendrea V. Shenoy, , William Nicholls- Synopsys, Inc., Mountain View, CA ********************************************************************************** Session: 39 | Title: System on Chip Design Time: 8:30 to 10:00 | RM : 288 Chair: Rolf Ernst - Tech. Univ. of Braunschweig, Braunschweig, DEU Organizers: Krzysztof Kuchcinski, Miodrag Potkonjak SoC is the enabling technology that will close the gap between exponentially growing silicon potential and designers productivity. In modern design, memory most often dominate transistor budget. The first paper proposes solution to smoothly integrate embedded memories in complex SoCs. The second paper introduces a revolutionary protocol design technique which enables exptional improvements on industrial design. Final two papers address focused but important problems in System design: efficient use of background memory and design of multiprecision circuit. 39.1 Automatic Generation of Embedded Memory Wrapper for Multiprocessor SoC Speaker: Ferid Gharsalli, - TIMA Lab. Authors:Ferid Gharsalli, Samy Meftali, Frederic Rousseau, , Ahmed Jerraya, - TIMA Lab., Grenoble, France 39.2 A Novel Synthesis Technique for Communication Controller Hardware from Declarative Data Communication Protocol Specifications Speaker: Robert Siegmund, - Tech. Univ. of Chemnitz Authors:Robert Siegmund, , Dietmar Müller- Tech. Univ. of Chemnitz, Chemnitz, Germany 39.3s An Integrated Algorithm for Memory Allocation and Assignment in High-Level Synthesis Speaker: Jaewon Seo, - KAIST Authors:Jaewon Seo, , Taewhan Kim- KAIST, Taejon, Korea, , Preeti R. Panda- Synopsys, Inc., Mountain View, CA 39.4s High-Level Synthesis of Multiple-Precision Circuits Independent of Data-Objects Length Speaker: Maria C. Molina, - Complutense Univ. Authors:Maria C. Molina, Jose M. Mendias, , Roman Hermida- Complutense Univ., Madrid, Spain ********************************************************************************** Session: 40 | Title: Timing Analysis and Memory Optimization for Embedded Systems Time: 8:30 to 10:00 | RM : 287 Chair: Giuseppe Lipari - Scuola S. Anna, Pisa, ITA Organizers: Marco Di Natale, Xiaobo Sharon Hu High performance embedded systems present many design challenges, e.g., timing analysis and memory management. Papers in this session introduce new techniques to tackle some of these challenges. The first paper presents a schedulability analysis algorithm for real-time systems. The second paper describes a technique to estimate execution time bounds with full consideration of cache effects. The last paper discusses optimization of scratch-pad memory. 40.1 Schedulability of Event-Driven Code Blocks in Real-Time Embedded Systems Speaker: Samarjit Chakraborty, - ETH Zurich Authors:Samarjit Chakraborty, Thomas Erlebach, Simon Kuenzli, , Lothar Thiele, - ETH Zurich, Zurich, Switzerland 40.2 Associative Caches in Formal Software Timing Analysis Speaker: Fabian Wolf, - Volkswagen AG Authors:Fabian Wolf - Volkswagen AG, Wolfsburg, Germany, Jan Staschulat, , Rolf Ernst- Tech. Univ. of Braunschweig, Braunschweig, Germany 40.3 Compiler-Directed Scratch Pad Memory Hierarchy Design and Management Speaker: Alok Choudhary, - Northwestern Univ. Authors:Mahmut T. Kandemir - Penn State Univ., University Park, PA, , Alok Choudhary- Northwestern Univ., Evanston, PA ********************************************************************************** Session: 41 | Title: Processors and Accelerators for Embedded Applications Time: 10:30 to 12:00 | RM : Auditorium B Chair: Chris Rowen - Tensilica, Santa Clara, CA Organizers: Kurt Keutzer, Majid Sarrafzadeh The papers in this session explore the design challenges associated with taking an embedded application all the way to silicon. The first paper explores the design of a Rijndael processor. The second looks at a contemporary embedded processor design. Each of these two designs probes the state-of-the-art in performance. The third paper reviews architectural and micro-architectural issues in the development of an accelerator for network applications. 41.1 Unlocking the Design Secrets of a 2.29 Gb/s Rijndael Processor Speaker: Patrick R. Schaumont, - Univ. of California Authors:Patrick R. Schaumont, Henry Kuo, , Ingrid Verbauwhede- Univ. of California, Los Angeles, CA 41.2 The iCOREtm 520 MHz Synthesizable CPU Core Speaker: Naresh Soni, - STMicroelectronics Authors:Naresh Soni - STMicroelectronics, San Diego, CA 41.3 A Flexible Accelerator for Layer 7 Networking Applications Speaker: Gokhan Memik, - Univ. of California Authors:Gokhan Memik, , Bill Mangione Smith- Univ. of California, Los Angeles, CA ********************************************************************************** Session: 42 | Title: PANEL: What is the Next EDA Driver? Time: 10:30 to 12:00 | RM : Auditorium A Chair: Jan Rabaey - Univ. of California, Berkeley, CA Organizers: As designers struggle with developing application solutions consisting of complex systems-on-a-chip with a significant software component, they must deal with a diversity of tools with very different philosophies and assumptions, to help manage this task. On one hand are tools which assume a clean separation between the hardware and software parts of the design with an abstraction of the hardware available for software development. On the other hand are tools that try to handle the hardware and software parts of the design concurrently. What drives these different philosophies? Which of these is critical for emerging system designs? Which of these is viable going forward? Our panel of experts consisting of designers, embedded software tool providers, system design tool providers and an academic will answer these challenging questions. 42.1 What's the New EDA Driver? Speaker: Raul Camposano, - Synopsys, Inc.Vassilios Gerousis, - Infineon TechnologiesLarry Lerner, - Agilent TechnologiesHans Spanjaart, - Philips SemiconductorsPierre Paulin Authors: ********************************************************************************** Session: 43 | Title: Cross-Talk Noise Analysis and Management Time: 10:30 to 12:00 | RM : 292 Chair: Cheng-Kok Koh - Purdue Univ., West Lafayette, IN Organizers: Kaushik Roy, Noel Menezes With the scaling of technology, cross-talk noise is becoming increasingly important. The papers in this session describe techniques to analyze and estimate cross-talk noise effects and present routing tools which consider cross-talk as a constraint. 43.1 Estimation of the Likelihood of Capacitive Coupling Noise Speaker: Sarma Vrudhula, - Univ. of Arizona Authors:Sarma Vrudhula - Univ. of Arizona, Tucson, AZ, , David Blaauw- Univ. of Michigan, Ann Arbor, MI, , Supamas Sirichotiyakul- Sun Microsystems, Boston, MA 43.2 Crosstalk Noise Estimation for Noise Management Speaker: Paul B. Morton, - Univ. of California Authors:Paul B. Morton, , Wayne Dai- Univ. of California, Santa Cruz, CA 43.3s Variable Frequency Crosstalk Noise Analysis: A Methodology to Guarantee Functionality from DC to FMAX Speaker: Byron Krauter, - IBM Corp. Authors:Byron Krauter, , David J. Widiger- IBM Corp., Austin, TX 43.4s Towards Global Routing With RLC Crosstalk Constraints Speaker: Lei He, - Univ. of Wisconsin Authors:James Ma, , Lei He- Univ. of Wisconsin, Madison, WI ********************************************************************************** Session: 44 | Title: Test Cost Reduction for SoCs Time: 10:30 to 12:00 | RM : 288 Chair: Yervant Zorian - Virage Logic Inc., Fremont, CA Organizers: Seiji Kajihara The papers in this session focus on test cost reduction for SoC designs. The proposed test compression and scheduling methods bring siginifcant reduction of test application time, test data volume and/or power dissipation during testing. The first paper describes a method of encoding test data. The second paper presents control schemes for testing embedded cores. The last paper describes an integrated framework for SOC test automation. 44.1 Reduction of SOC Test Data Volume, Scan Power and Testing Time Using Alternating Run-length Codes Speaker: Anshuman Chandra, - Duke Univ. Authors:Anshuman Chandra, , Krishnendu Chakrabarty- Duke Univ., Durham, NC 44.2 Embedded Test Control Schemes for Compression in SoCs Speaker: Douglas Kay, - Cisco Systems, Inc. Authors:Douglas Kay, , Sung Chung- Cisco Systems, Inc., San Jose, CA, , Samiha Mourad- Santa Clara Univ., Santa Clara, CA 44.3 Integrated Wrapper/TAM Co-Optimization, Constraint-Driven Test Scheduling, and Tester Data Volume Reduction for SOCs Speaker: Vikram Iyengar, - Duke Univ. Authors:Vikram Iyengar, , Krishnendu Chakrabarty- Duke Univ., Durham, NC, , Erik Jan Marinissen- Philips Research Labs., Eindhoven, The Netherlands ********************************************************************************** Session: 45 | Title: Scheduling Techniques for Embedded Systems Time: 10:30 to 12:00 | RM : 287 Chair: Rolf Ernst - Tech. Univ. of Braunschweig, Braunschweig, DEU Organizers: Diederik Verkest, Donatella Sciuto More and more embedded systems contain multiple on-chip processors and memory and are often battery powered. In these systems energy efficiency is of extreme importance. This session combines papers that look at how scheduling can influence power dissipation in all parts of the system. The first paper looks at how to better parallelize an application on a multi-processor architecture. The second paper looks at how an OS scheduler can direct DRAM power mode management. The last paper investigates the influence of scheduling on battery lifetime. 45.1 Communication Based Power Management for Battery Efficient System Design Speaker: Kanishka Lahiri, - Univ. of California at San Diego Authors:Kanishka Lahiri - Univ. of California at San Diego, La Jolla, CA, , Anand raghunathan- NEC Corp., Princeton, NJ, , Sujit Dey- Univ. of California at San Diego, La Jolla, CA 45.2 Scheduler-Based DRAM Energy Management Speaker: Victor M. De La Luz, - Penn State Univ. Authors:Victor M. De La Luz, Anand Sivasubramaniam, Mahmut T. Kandemir, Vijaykrishnan Narayanan, , Mary Jane Irwin, - Penn State Univ., University Park, PA 45.3 An Integer Linear Programming Based Approach for Parallelizing Applications in On-Chip Multiprocessors Speaker: Ismail Kadayif, - Penn State Univ. Authors:Ismail Kadayif, , Mahmut T. Kandemir- Penn State Univ., University Park, PA, , Ugur Sezer- Univ. of Wisconsin, Madison, WI ********************************************************************************** Session: 46 | Title: SPECIAL SESSION: Designing SoCs for Yield Improvement Time: 2:00 to 4:00 | RM : Auditorium B Chair: Srivaths Ravi - NEC USA, Princeton, NJ Organizers: Anand Raghunathan The increasing scale and complexity of System-on-Chips, together with the emergence of new failure mechanisms in nanometer technologies, poses serious challenges to various steps of the SoC manufacturing process, including manufacturing test, defect diagnosis, yield enhancement, and reliability improvement. Conventional approaches to address these issues are giving way to solutions that increasingly involve special IP blocks embedded in the SoCs (called infrastructure IP) to help with the above steps. The first presentation will focus on how infrastructure IPs can be used to address various manufacturing challenges, ranging from manufacturing test and silicon debug to improving yield and reliability. The second presentation addresses a recent and growing trend in SoCs - the use of embedded reconfigurable logic. It covers the self-test, diagnosis, and repair for yield improvement of embedded FPGAs, and outlines how they can be used to test other embedded cores. 46.1 Embedding Infrastructure IP for SoC Yield Improvement Speaker: Yervant Zorian, - Virage Logic Inc.Charles Stroud, - Univ. of North Carolina Authors:Yervant Zorian - Virage Logic Inc., Fremont, CA, , Charles Stroud- Univ. of North Carolina, Charlotte, NC, , Marty Emmert- Wright State Univ., Dayton, OH 46.2 Using Embedded FPGAs for SoC Yield Improvement Speaker: Miron Abramovici, - Agere Systems, Inc. Authors:Miron Abramovici - Agere Systems, Inc., Murray Hill, NJ, , Charles Stroud- Univ. of North Carolina, Charlotte, NC, , Marty Emmert- Wright State Univ., Dayton, OH ********************************************************************************** Session: 47 | Title: Advances in SAT Time: 2:00 to 4:00 | RM : Auditorium A Chair: Joao Marques-Silva - IST/INESC, Lisboa,