Session: 1 | Title: Special Session: Real Challenges and Solutions for Validating System-on-Chip Time: 10:30 to 12:00 | RM : AB Chair: Wolfgang Rosenstiel - Univ. of Tubingen, Tubingen, DEU Organizers: The first paper will discuss the application of FPV to the validation of the Pentium® 4 microarchitecture. New approaches are considered to broaden the application of FV techniques, particularly at higher abstraction levels. GSTE and SAT will significantly increase the scope of what can be formally verified. Second, the verification strategy for the integration of a multi-processors baseband chip for the 3G wireless phone market is presented. Examples and metrics illustrate the key design challenges of large SoC verification, enhancement opportunities are explored. Last, but not least, the development of large servers is facing multiple challenges like mixing design styles from custom VLSI to ASIC and SoC designs, including various IP as well as a combination of hardware and firmware. 1.1 High-Level Formal Verification of Next-Generation Microprocessors Speaker: Tom Schubert, - Intel Corp. Authors:Tom Schubert - Intel Corp., Hillsboro, OR 1.2 Verification Strategy for Integrating 3G Baseband SoC Speaker: Yves Mathys, - Motorola, Inc. Authors:Yves Mathys, , Andre Chatelain- Motorola, Inc., Geneva, Switzerland 1.3 Improvements in Functional Simulation Addressing Challenges in Large, Distributed Industry Projects Speaker: Klaus-Dieter Schubert, - IBM Corp. Authors:Klaus-Dieter Schubert - IBM Corp., Boeblingen, Germany ********************************************************************************** Session: 2 | Title: Panel: Reshaping EDA for Power Time: 10:30 to 12:00 | RM : 207ABCD Chair: Jan Rabaey - Univ. of California, Berkeley, CA Organizers: Dennis Sylvester Today's rising power densities are reminiscent of the end of the bipolar design era twenty years ago and are widely cited as the foremost challenge to continued CMOS scaling. On a more optimistic note, the power bottleneck provides excellent opportunities for EDA innovation in areas such as leakage reduction, power distribution, and low-power clocking. This panel brings together experts in circuit design and CAD tool development to discuss the current status of low-power EDA offerings and provide opinions on what new capabilities are most important in the power-constrained design era. 2.1 Reshaping EDA for Power Speaker: Mark Horowitz, - Stanford Univ.Andrew T. Yang, - Apache Design Solutions, Inc.Takayasu Sakurai, - Univ. of TokyoWolfgang Nebel, - Oldenburg Univ.Kerry Bernstein, - IBM Corp. Authors: ********************************************************************************** Session: 3 | Title: Design for Manufacturability and Global Routing Time: 10:30 to 12:00 | RM : 210CD Chair: Martin Wong - Univ. of Illinois, Urbana, IL Organizers: Charles J Alpert, Dennis Sylvester, Raymond Nijssen This session addresses manufacturability topics that become prominent in subwavelength lithography as well as issues relating to the prominence of global interconnections in IC performance. The first paper focuses on reducing the cost of making optical proximity corrections by manipulating commercial sizing tools. The second paper describes a first approach to limiting the impact of metal fill on circuit delay. The third paper proposes a new method to reduce congestion in global routing by avoiding unnecessary detours. The final presentation presents an example showing the relationship between architecture and physical design. 3.1 A Cost-Driven Lihographic Correction Methodology Based on Off-the-Shelf Sizing Tools Speaker: Puneet Gupta, - Univ. of California at San Diego Authors:Puneet Gupta, , Andrew B. Kahng- Univ. of California at San Diego, La Jolla, CA, Dennis Sylvester, , Jie Yang, - Univ. of Michigan, Ann Arbor, MI 3.2 Performance-Impact Limited Area Fill Synthesis Speaker: Yu Chen, - Univ. of California Authors:Yu Chen, , Puneet Gupta- Univ. of California, San Diego, CA 3.3s Improved Global Routing by Amplified Congestion Estimation Speaker: Raia T. Hadsell, - Binghamton Univ. Authors:Raia T. Hadsell - Binghamton Univ., Binghamton, NY, , Patrick H. Madden- State Univ. of New York, Binghamton, NY 3.4s Microarchitecture Evaluation With Physical Planning Speaker: Michail Romesis, - Univ. of California Authors:Jason Cong, Ashok Jagannathan, Glenn Reinman, , Michail Romesis, - Univ. of California, Los Angeles, CA ********************************************************************************** Session: 4 | Title: Design Analysis Techniques Time: 10:30 to 12:00 | RM : 210AB Chair: Michael Kishinevsky - Intel Corp., Hillsboro, OR Organizers: Ahmed A Jerraya, Steven Haynal This session addresses different design flows as well as design environments. The main focus is on high-level design issues and their role in the design process. The first issue will be design techniques for differential power analysis protection. The second topic is a methodology that uses a SystemC and a network simulation environment for the verification of a 802.11 MAC chip design. Finally the application of design patterns to hardware design is discussed. 4.1 Energy Aware Design Techniques for Differential Power Analysis Protection Speaker: Alberto Macii, - Politecnico di Torino Authors:Luca Benini - Univ. Di Bologna, Bologna, Italy, Alberto Macii, , Enrico Macii- Politecnico di Torino, Torino, Italy, Elvira Omerbegovic, - BullDAST s.r.l., Torino, Italy, , Massimo Poncino, - Univ. Di Verona, Verona, Italy, , Fabrizio Pro, - BullDAST s.r.l., Torino, Italy 4.2 A Timing-Accurate Modeling and Simulation Environment for Networked Embedded Systems Speaker: Franco Fummi, - Univ. Di Verona Authors:Franco Fummi - Univ. Di Verona, Verona, Italy, , Paolo Gallo- Telecom Italia Lab., Torino, Italy, Stefano Martini, , Giovanni Perbellini, - Embedded Systems Design Ctr., Verona, Italy, , Massimo Poncino, - Univ. Di Verona, Verona, Italy, , Fabio Ricciato, - Telecom Italia Lab., Torino, Italy 4.3 Application of Design Patterns for Hardware Design Speaker: Vytautas Stuikys, - Kaunas Univ. of Tech. Authors:Robertas Damasevicius, Giedrius Majauskas, , Vytautas Stuikys- Kaunas Univ. of Tech., Kaunas, Lithuania ********************************************************************************** Session: 5 | Title: Embedded Hardware Design Case Studies Time: 10:30 to 12:00 | RM : 209AB Chair: Chris Rowen - Tensilica, Inc., Santa Clara, CA Organizers: Grant E Martin, Kurt Keutzer, Pai Chou The range of embedded hardware design applications is extremely wide and this session illustrates it. The first paper comes from the student design competition and presents an interesting design approach for a portable secure embedded system. The second paper deals with the design of an advanced high performance memory system for embedded System-on-chip design. The final paper introduces a whole new application area and systematic design approach to DAC: light sensor components for embedded appliances. This is an exciting group of applications that illustrate the interaction between embedded design and methodologies. 5.1 STUDENT DESIGN CONTEST: Design Flow for HW / SW Acceleration Transparency in the ThumbPod Secure Embedded System Speaker: David Hwang, - Univ. of California Authors:David Hwang, Patrick Schaumont, Yi Fan, Alireza Hodjat, Bo Cheng LaiKazuo Sakiyama, Shenglin Yang, , Ingrid Verbauwhede, - Univ. of California, Los Angeles, CA 5.2 A Fully-Programmable Memory Management System Optimizing Queue Handling at Multi Gigabit Rates Speaker: George Kornaros, - Ellemedia Tech. Authors:George Kornaros, Ioannis Papaefstathiou, Aristidis Nikologiannis, , Nikolaos Zervos, - Ellemedia Tech., Athens, Greece 5.3 Design Techniques for Sensor Appliances: Foundations and Light Compass Case Study Speaker: Jennifer L Wong, - Univ. of California Authors:Jennifer L Wong, Seapahn Megerian, , Miodrag Potkonjak- Univ. of California, Los Angeles, CA ********************************************************************************** Session: 6 | Title: Special Session: Emerging Design and Tool Challenges in RF and Wireless Applications Time: 2:00 to 4:00 | RM : AB Chair: Georges Gielen - Katholieke Univ., Leuven, BEL Organizers: RF/wireless applications have emerged as important markets, driven by cellular and high-speed wireless data communications (e.g. 802.11 WLAN), but with other applications such as 4G communications, ambient intelligence and ubiquitous ad-hoc sensor networks looming on the horizon. This special session will address the challenges in terms of design capabilities, technology choices and design tools that are ahead of us to materialize these applications. Starting from the system requirements, an overview will be given of technology choices and design challenges that await the designers at both the system architectural level and the circuit level. Also new modeling and simulation tools for these systems will be discussed. 6.1 Seamless Multi-Radio Integration Challenges Speaker: Uri Barkai, - Intel Corp. Authors:Uri Barkai - Intel Corp., Petach-Tikva, Israel 6.2 RF Front End Application and Technology Trends Speaker: Pieter Hooijmans, - Philips Research Labs. Authors:Pieter Hooijmans - Philips Research Labs., Eindhoven, The Netherlands 6.3 4G-Terminals: How are We Going to Design Them? Speaker: Jan Craninckx, - IMEC Authors:Jan Craninckx, , Stephane Donnay- IMEC, Leuven, Belgium 6.4 New Techniques for Non-Linear Behavioral Modeling of Microwave/RF ICs from Simulation and Nonlinear Microwave Measurements Speaker: David E. Root, - Agilent Technologies Authors:David E. Root, , John Wood- Agilent Technologies, Santa Rosa, CA, , Nick Tufillaro- Agilent Labs., Palo Alto, CA ********************************************************************************** Session: 7 | Title: Panel: COT - Customer Owned Trouble? Time: 2:00 to 4:00 | RM : 207ABCD Chair: Bob Dahlberg - Reshape, Inc., Mountain View, CA Organizers: Increasingly, system houses are attracted to the COT model to gain more control on their schedules and cost. The pathways to implement a COT design include (a) Manage the sourcing (internal or third party resources) of individual supply chain and cost reduction functions (b) Use an integrated design-to-parts service or (c) A hybrid of these two extremes. COT project risk and cost are high, so the design team needs to be expertly prepared. This panel will consider the pros and cons for each approach. 7.1 COT - Customer Owned Trouble? Speaker: Kaushik Patel, - Azanda Network DevicesPaul Ruddy, - Cisco SystemsAurangzeb Khan, - Cadence Design Systems, Inc.Naveed Sherwani, - Open Silicon, Inc.Ronnie Vasishta, - LSI Logic Authors: ********************************************************************************** Session: 8 | Title: Power Grid Analysis and Optimization Time: 2:00 to 4:00 | RM : 210CD Chair: Sani Nassif - IBM Corp., Austin, TX Organizers: Abhijit Dharchoudhury, Anirudh Devgan CMOS scaling is leading to a reduction in the power supply voltage and a simultaneous increase in the on-chip power density. This trend mandates increased focus on power grid signal integrity. This session deals with exciting new approaches in the analysis and optimization of on-chip power networks. The first paper presents a technique for static power drop estimation, followed by two papers on power grid analysis using algebraic multi-grid techniques. Fourth paper addresses impact of leakage on the supply integrity. The last paper presents techniques for optimizing the power distribution network. 8.1 Random Walks in a Supply Network Speaker: Haifeng Qian, - Univ. of Minnesota Authors:Haifeng Qian - Univ. of Minnesota, Minneapolis, MN, , Sani R. Nassif- IBM Corp., Austin, TX, , Sachin S. Sapatnekar- Univ. of Minnesota, Minneapolis, MN 8.2 A Static Pattern-Independent Technique for Power Grid Voltage Integrity Verification Speaker: Dionysios Kouroussis, - Univ. of Toronto Authors:Dionysios Kouroussis, , Farid N. Najm- Univ. of Toronto, Toronto, ON, Canada 8.3s Power Network Analysis Using an Adaptive Algebraic Multigird Approach Speaker: Zhengyong Zhu, - Univ. of California at San Diego Authors:Zhengyong Zhu, Bo Yao, , Chung-Kuan Cheng- Univ. of California at San Diego, La Jolla, CA 8.4s Power Grid Reduction Based on Algebraic Multigrid Principles Speaker: Haihua Su, - IBM Corp. Authors:Haihua Su, Emrah Acar, , Sani R. Nassif- IBM Corp., Austin, TX 8.5 On-chip Power Supply Network Optimization using Multigrid-based Technique Speaker: Kai Wang, - Univ. of California Authors:Kai Wang, , Malgorzata Marek-Sadowska- Univ. of California, Santa Barbara, CA ********************************************************************************** Session: 9 | Title: Low-Power Embedded System Design Time: 2:00 to 4:00 | RM : 210AB Chair: Rajesh K. Gupta - Univ. of California at San Diego, San Diego, CA Organizers: Diederik Verkest, Taewhan Kim The session presents papers in embedded low power system design considering various design aspects such as variable voltage scaling, memory organization for low power, and power management using component mode transitions. 9.1 Scalable Modeling and Optimization of Mode Transitions Based on Decoupled Power Management Architecture Speaker: Dexin Li, - Univ. of California Authors:Dexin Li, Qiang Xie, Pai H. Chou, , Nader Bagherzadeh, - Univ. of California, Irvine, CA 9.2 Optimal Voltage Allocation Techniques for Dynamically Variable Voltage Processors Speaker: Woo-Cheol Kwon, - Samsung Electronics Co., Ltd. Authors:Woo-Cheol Kwon - Samsung Electronics Co., Ltd., Yong-in, Republic of Korea, , Taewhan Kim- KAIST, Daejon, Republic of Korea 9.3 Energy Reduction Techniques for Multimedia Applications with Tolerance to Deadline Misses Speaker: Shaoxiong Hua, - Univ. of Maryland Authors:Shaoxiong Hua, Gang Qu, , Shuvra Bhattacharyya- Univ. of Maryland, College Park, MD 9.4 Xtream-Fit: An Energy-Delay Efficient Data Memory Subsystem for Embedded Media Processing Speaker: Anand Ramachandran, - Univ. of Texas Authors:Anand Ramachandran, , Margarida F. Jacome- Univ. of Texas, Austin, TX ********************************************************************************** Session: 10 | Title: Cyclic and Non-Cyclic Combinational Circuit Synthesis Time: 2:00 to 4:00 | RM : 209AB Chair: Victor Kravets - IBM Corp., Yorktown Heights, NY Organizers: Marek Perkowski, Soha Hassoun This session addresses logic minimization. The first paper presents a practical enhancements to recently proposed constructive decomposition. The second paper proposes a new approach to SOP minimization basd on decomposition. The third paper explores novel general cofactoring for for multi-valued functions to speed functional evaluation. The last two papers address combinational optimizations for cyclic circuits. 10.1 A New Enhanced Constructive Decomposition and Mapping Algorithm Speaker: Alan Mishchenko, - Univ. of California Authors:Alan Mishchenko - Univ. of California, Berkeley, CA, Xinning Wang, , Timothy Kam- Intel Corp., Hillsboro, OR 10.2 Large-Scale SOP Minimization Using Decomposition and Functional Properties Speaker: Tsutomu Sasao, - Kyushu Institute of Tech. Authors:Alan Mishchenko - Univ. of California, Berkeley, CA, , Tsutomu Sasao- Kyushu Institute of Tech., Fukuoka, Japan 10.3s Generalized Cofactoring for Logic Function Evaluation Speaker: Yunjian Jiang, - Univ. of California Authors:Yunjian Jiang, Slobodan Matic, , Robert K. Brayton- Univ. of California, Berkeley, CA 10.4s Making Cyclic Circuits Acyclic Speaker: Stephen A. Edwards, - Columbia Univ. Authors:Stephen A. Edwards - Columbia Univ., New York, NY 10.5 The Synthesis of Cyclic Combinational Circuits Speaker: Marc D. Riedel, - Caltech Authors:Marc D. Riedel, , Jehoshua Bruck- Caltech, Pasadena, CA ********************************************************************************** Session: 11 | Title: Managing Leakage Power Time: 4:30 to 6:30 | RM : AB Chair: Siva Narendra - Intel Corp., Hillsboro, OR Organizers: Renu Mehra Leakage power consumption is projected to be one of the most dominant power components in very deep-submicron technologies. Papers in this session address different issues related to leakage power estimation and minimization. 11.1 Accurate Estimation of Total Leakage Current in Scaled CMOS Logic Circuits Based on Compact Current Modeling Speaker: Saibal Mukhopadhyay, - Purdue Univ. Authors:Saibal Mukhopadhyay, Arijit Raychowdhury, , Kaushik Roy- Purdue Univ., West Lafayette, IN 11.2 Analysis and Minimization Techniques for Total Leakage Considering Gate Oxide Leakage Speaker: Dongwoo Lee, - Univ. of Michigan Authors:Dongwoo Lee, Wesley Kwong, Dennis Sylvester, , David Blaauw, - Univ. of Michigan, Ann Arbor, MI 11.3 Distributed Sleep Transistor Network for Power Reduction Speaker: Changbo Long, - Univ. of Wisconsin Authors:Changbo Long - Univ. of Wisconsin, Madison, WI, , Lei He- Univ. of California, Los Angeles, CA 11.4s Implications of Technology Scaling on Leakage Reduction Techniques Speaker: Yuh-Fang Tsai, - Penn State Univ. Authors:Yuh-Fang Tsai - Penn State Univ., University Park, PA, , David Duarte- Intel Corp., Portland, OR, Vijaykrishnan N., , Mary J. Irwin, - Penn State Univ., University Park, PA 11.5s Static Leakage Reduction through Simultaneous Threshold Voltage and State Assignment Speaker: David Blaauw, - Univ. of Michigan Authors:Dongwoo Lee, , David Blaauw- Univ. of Michigan, Ann Arbor, MI ********************************************************************************** Session: 12 | Title: Panel: Emerging Markets: Design Goes Global Time: 4:30 to 6:30 | RM : 207ABCD Chair: Chi Foon Chan - Synopsys, Inc., Mountain View, CA Organizers: China and India represent two of the most rapidly evolving markets for IC design today. According to the CMP China IC Design Survey 2002, demand for IC design services in China is growing exponentially alongside 8- and 12-inch wafer fab construction. In India, multinationals and local companies continue to accelerate the development of complex IC’s, matching the sophistication of design teams world wide. China and India are graduating the most EEs annually of any other countriess. This dynamic growth of IC design and its associated infrastructure in China & India is causing is causing all participants in the semiconductor value chain to carefully consider their business interactions in these countries. This panel will evaluate how IC design is changing in these emerging markets. Panelists will represent a variety of viewpoints, including multinationals, local government, local universities, and large local companies. The panel will also explore of this emerging market on the EDA industry. 12.1 Emerging Markets: Design Goes Global Speaker: Mahesh Mehendale, - Texas InstrumentsA. Vasudevan, - Wipro Tech.Michael Chen, - Pericom Semiconductor Corp.Robert Yung, - Intel Corp. Authors: ********************************************************************************** Session: 13 | Title: Timing-Oriented Placement Time: 4:30 to 6:30 | RM : 210CD Chair: Ralph Otten - Eindhoven Univ. of Tech., Eindhoven, NLD Organizers: C Y Roger Chen, Carl Sechen Since delay is an increasingly important issue in chip design, emphasis is shifting from area and wire length towards timing. Delay budgeting and retiming have found their place in design trajectory, but integration with placement is very much a topic of today. Also the possibility of logic replication in order to meet timing constraints will be considered in this session. Once the timing requirements can be formulated as constraints on nets, powerful tool combinations can provide high quality placements. 13.1 Timing Optimization of FPGA Placements by Logic Replication Speaker: Giancarlo Beraudo, - Univ. of Illinois Authors:Giancarlo Beraudo, , John Lillis- Univ. of Illinois, Chicago, IL 13.2 Delay Budgeting in Sequential Circuits with Application to FPGA Placement Speaker: Chao-Yang Yeh, - Univ. of California Authors:Chao-Yang Yeh, , Malgorzata Marek-Sadowska- Univ. of California, Santa Barbara, CA 13.3 Multilevel Global Placement with Retiming Speaker: Xin Yuan, - Univ. of California Authors:Jason Cong, , Xin Yuan- Univ. of California, Los Angeles, CA 13.4 Force Directed Mongrel with Physical Net Constraints Speaker: Bill Halpin, - Intel/Syracuse Univ. Authors:Tung Cao - Intel Corp., Santa Clara , CA, , Sung Hur- Syracuse Univ., Syracuse, NY, , Amit Chowdhary- Intel Corp., Santa Clara, CA, Bill Halpin, - Intel/Syracuse Univ., Santa Clara, CA, Yegna ParasuramKarthik Rajagopal, , Vladimir Tiourin, - Intel Corp., Santa Clara, CA ********************************************************************************** Session: 14 | Title: Model Order Reduction Time: 4:30 to 6:30 | RM : 210AB Chair: Frank Liu - IBM Corp., Austin, TX Organizers: Sachin S Sapatnekar Model order reduction is a critical component in CAD extraction and verification. The first two papers focus on realizable reduction of RLCK networks. The third paper proposes a novel reduction method incorporating skin effect, and the final paper addresses modeling of nonuniform transmission lines. 14.1 Realizable Parasitic Reduction Using Generalized Y-Δ Transformation Speaker: Zhanhai Qin, - Univ. of California at San Diego Authors:Zhanhai Qin, , C.K. Cheng- Univ. of California at San Diego, La Jolla, CA 14.2 Realizable RLCK Circuit Crunching Speaker: Chirayu S. Amin, - Northwestern Univ. Authors:Chirayu S. Amin, Masud H. Chowdhury, , Yehea I. Ismail- Northwestern Univ., Evanston, IL 14.3 Efficient Model Order Reduction Including Skin Effect Speaker: Shizhong Mei, - Northwestern Univ. Authors:Shizhong Mei, Chirayu Amin, , Yehea I. Ismail- Northwestern Univ., Evanston, IL 14.4 Model Order Reduction of Nonuniform Transmission Lines Using Integrated Congruence Transform Speaker: Emad F. Gad, - Carleton Univ. Authors:Emad F. Gad, , Michel Nakhla- Carleton Univ., Ottawa, ON, Canada ********************************************************************************** Session: 15 | Title: Issues in Partitioning and Design Space Exploration for Codesign Time: 4:30 to 6:30 | RM : 209AB Chair: Nikil Dutt - Univ. of California, Irvine, CA Organizers: Donatella Sciuto The first paper presents a system level approach to simplify task scheduling by grouping tasks which should be executed on the same resource. The second paper presents run-time partitioning where software is monitored and possible dynamically translated into hardware, based on monitoring and synthesis algorithms placed in hardware. Third paper performs instruction set extension based on capabilities provided by the processor architecture. The fourth paper presents generation of abstract instruction encodings needed for software tool generation during architecture exploration. 15.1 Partial Task Assignment of Task Graphs under Heterogeneous Resource Constraints Speaker: Radoslaw W. Szymanek, - Lund Univ. Authors:Radoslaw W. Szymanek, , Krzysztof Kuchcinski- Lund Univ., Lund, Sweden 15.2 Dynamic HW/SW Partitioning: A First Approach Speaker: Greg M. Stitt, - Univ. of California Authors:Greg M. Stitt, Roman Lysecky, , Frank Vahid- Univ. of California, Riverside, CA 15.3 Automatic Application-Specific Instruction-Set Extensions under Microarchitectural Constraints Speaker: Kubilay Atasu, - Swiss Federal Institute of Tech. Authors:Kubilay Atasu, Laura Pozzi, , Paolo Ienne- Swiss Federal Institute of Tech., Lausanne, Switzerland 15.4 Instruction Encoding Synthesis for Architecture Exploration using Hierarchical Processor Models Speaker: Achim Nohl, - CoWare, Inc. Authors:Achim Nohl, Volker Greive, Gunnar Braun, , Andreas Hoffmann, - CoWare, Inc., San Jose, CA, Rainer LeupersOliver Schliebusch, , Heinrich Meyr, - Aachen Univ. of Tech., Aachen, Germany ********************************************************************************** Session: 16 | Title: Special Session: Nano Technology: Design Implications and CAD Challenges Time: 8:30 to 10:00 | RM : AB Chair: Rolf Ernst - Technical Univ. of Braunsweig, Braunsweig, DEU Organizers: Nano technology and devices will have revolutionary impact on the CAD field. Similarly, CAD research at circuit, logic and architectural levels for nano devices can provide valuable feedbacks to nano research and illuminate ways for developing new nano devices. It is time for CAD researchers to play an active role in nano research. This special session aims to arouse the interests of CAD researchers in more ``revolutionary'' types of nano devices. It brings together a group of industry and academia experts to review latest advances in molecular electronics and discuss design implications and CAD challenges introduced by nano devices. 16.1 Quantum-dot Cellular Automata: Computing by Polarized Systems Speaker: Gary H. Bernstein, - Univ. of Notre Dame Authors:Gary H. Bernstein - Univ. of Notre Dame, Notre Dame, IN 16.2 Recent Advances and Future Prospects in Single-Electronics Speaker: Christoph Wasshuber, - Texas Instruments, Inc. Authors:Christoph Wasshuber - Texas Instruments, Inc., Dallas, TX 16.3 Manipulation and Characterization of Molecular Scale Components Speaker: Islamshah Amlani, - Motorola, Inc. Authors:Islamshah Amlani - Motorola, Inc., Tempe, AZ ********************************************************************************** Session: 17 | Title: Panel: Mixed Signals on Mixed-Signal: The Right Next Technology Time: 8:30 to 10:00 | RM : 207ABCD Chair: Rob A. Rutenbar - Carnegie Mellon Univ., Pittsburgh, PA Organizers: CMOS dominates digital microelectronics. However, wireless applications require RF circuits at 1-5GHz, and exotic higher frequency applications are on the horizon. Silicon-Germanium (SiGe) is a growing choice for these designs. But is it "the" answer? Some argue that scaled CMOS will handle all tomorrow's RF ICs. Others argue that one-chip SoC solutions will never be the winning strategy for these highly heterogeneous designs, and place their bets on system-in-package (SiP) technologies. Is there a right answer here? Is CMOS the "only" way, or just "another" way? 17.1 Mixed Signals on Mixed-Signal: The Right Next Technology Speaker: Raminderpal Singh, - IBM Corp.Kurt Johnson, - Cadence Design Systems, Inc.Paul Kempf, - Jazz SemiconductorTeresa Meng, - Stanford Univ./Atheros CommunicationsReza Rofougaran, - Broadcom Authors: ********************************************************************************** Session: 18 | Title: Simulation Coverage and Generation for Verification Time: 8:30 to 10:00 | RM : 210CD Chair: Umberto Rossi - STMicroelectronics, Agrate Brianza, ITA Organizers: Hikeung T Ma, Shin-ichi Minato Coverage of assertions, source code, FSMs and other measures is common in the industry. The first three papers of this session deal with interesting ways of measuring coverage and industrial experience. The last paper deals with an algorithm to generate simulation vectors in a constrained random way. 18.1 Coverage-Oriented Verification of Banias Speaker: Alon Gluska, - Intel Corp. Authors:Alon Gluska - Intel Corp., Haifa, Israel 18.2 Coverage Directed Test Generation for Functional Verification using Bayesian Networks Speaker: Shai Fine, - IBM Haifa Research Lab. Authors:Shai Fine, , Avi Ziv- IBM Haifa Research Lab., Haifa, Israel 18.3s Dos and Don'ts of CTL State Coverage Estimation Speaker: Nikhil Jayakumar, - Univ. of Colorado Authors:Nikhil Jayakumar, Mitra Purandare, , Fabio Somenzi- Univ. of Colorado, Boulder, CO 18.4s Constraint Synthesis for Environment Modeling in Functional Verification Speaker: Jun Yuan, - Motorola, Inc. Authors:Jun Yuan - Motorola, Inc., Austin, TX, , Adnan Aziz- Univ. of Texas, Austin, TX, , Carl Pixley- Synopsys, Inc., Hillsboro, OR, Ken Albin, - Motorola, Inc., Austin, TX ********************************************************************************** Session: 19 | Title: Tool Support for Architectural Decisions in Embedded Systems Time: 8:30 to 10:00 | RM : 210AB Chair: Grant E. Martin - Cadence Design Systems, Inc., Berkeley, CA Organizers: Grant E Martin, Kurt Keutzer, Pai Chou Architects and micro-architects face a vast number of decisions in the development of embedded systems. Software tools have the potential to play a significant role in informing these decisions. This session describes tools that address three different problems in developing embedded architectures. The first paper addresses the high-level problem of refining communication at the application-level on to underlying communication structures. The second paper describes a tool for examining different approaches to code compression. The third paper looks at a tool for evaluating bus-scheduling approaches. 19.1 Automatic Communication Refinement for System Level Design Speaker: Samar Abdi, - Univ. of California Authors:Samar Abdi, Dongwan Shin, , Daniel D. Gajski- Univ. of California, Irvine, CA 19.2 CoCo: A Hardware/Software Platform for Rapid Prototyping of Code Compression Technologies Speaker: Haris Lekatsas, - NEC Corp. Authors:Haris Lekatsas - Vorras Corp., Princeton, NJ, Joerg Henkel, Srimat Chakradhar, Venkata Jakkula, , Murugan Sankaradass, - NEC Corp., Princeton, NJ 19.3 A Tool for Describing and Evaluating Hierarchial RealTime Bus Scheduling Policies Speaker: Trevor C. Meyerowitz, - Univ. of California Authors:Trevor C. Meyerowitz, Claudio Pinello, , Alberto L. Sangiovanni-Vincentelli- Univ. of California, Berkeley, CA ********************************************************************************** Session: 20 | Title: New Topics in Logic Synthesis Time: 8:30 to 10:00 | RM : 209AB Chair: Shigeru Yamashita - NTT Communication Science Labs., Kyoto, JPN Organizers: Marek Perkowski, Steven M Nowick The papers in this session explore new topics in logic synthesis. The first paper explores synthesizing optimal two-qubit quantum circuits. The second paper presents novel algorithms for synthesizing reversible circuits in terms of n x n Toffoli gates. The third paper advocates using PLI to model asynchronous circuits at the behavioral level. The final paper describes an algorithm and applications (routing table reductions and access control list reduction) for dynamic on-chip logic minimization. 20.1 A Transformation Based Algorithm for Reversible Logic Synthesis Speaker: Gerhard W. Dueck, - Univ. of New Brunswick Authors:D. Michael Miller - Univ. of Victoria, Victoria, BC, Canada, Dmitri Maslov, , Gerhard W. Dueck- Univ. of New Brunswick, Fredericton, NB, Canada 20.2 Implementing An Arbitrary Two-qubit Computation In 23 Elementary Gates Or Less Speaker: Igor L. Markov, - Univ. of Michigan Authors:Igor L. Markov, , Stephen S. Bullock- Univ. of Michigan, Ann Arbor, MI 20.3s Verilog HDL, Powered by PLI: a Suitable Framework for Describing and Modeling Asynchronous Circuits at All Levels of Abstraction Speaker: Arash Saifhashemi, - Amirkabir Univ. of Tech. Authors:Arash Saifhashemi, , Hossein Pedram- Amirkabir Univ. of Tech., Tehran, Iran 20.4s On-Chip Logic Minimization Speaker: Roman Lysecky, - Univ. of California Authors:Roman Lysecky, , Frank Vahid- Univ. of California, Riverside, CA ********************************************************************************** Session: 21 | Title: Special Session: Coping with Variability: The End of Deterministic Design Time: 10:30 to 12:00 | RM : AB Chair: Michael Orshansky - Univ. of California, Berkeley, CA Organizers: Kurt Keutzer Tool developers and designers may have thought that after successively facing the challenges of timing closure, deep sub-micron effects, and power problems, they were due for a rest. But this session indicates that increasing process variability may have a more profound impact on tools and design methodology than any of these prior challenges. The first paper defines elements of process variability and discusses the relative magnitudes of their deleterious effects. The second indicates a series of tool and methodology challenges that must be faced if variability is to be managed. The third paper describes technical advances on statistical approaches to modeling timing. 21.1 Parameter Variations and Impact on Circuits & Microarchitecture Speaker: Shekhar Borkar, - Intel Corp. Authors:Shekhar Borkar, Tanay Karnik, Siva Narendra, Jim Tschanz, Ali Keshavarzi, Vivek De, - Intel Corp., Hillsboro, OR 21.2 Death, Taxes and Failing Chips Speaker: Chandu Visweswariah, - IBM Corp. Authors:Chandu Visweswariah - IBM Corp., Yorktown Heights, NY 21.3 Computation and Refinement of Statistical Bounds on Circuit Delay Speaker: Aseem B. Agarwal, - Univ. of Michigan Authors:Aseem B. Agarwal, , David Blaauw- Univ. of Michigan, Ann Arbor, MI, , Vladimir Zolotov- Motorola, Inc., Austin, TX, Sarma Vrudhula, - Univ. of Arizona, Tucson, AZ ********************************************************************************** Session: 22 | Title: Panel: Cheap Submicron: The Next Implementation Fabric/An IEEE D&T Feature Panel Time: 10:30 to 12:00 | RM : 207ABCD Chair: Abbas El Gamal - Stanford Univ., Stanford, CA Organizers: The semiconductor industry is caught on two horns of the economic dilemma: economics of technology, and economics of design productivity. Today, design is slow, expensive, and out of control. What next-generation fabric will restore cost-effective implementation? The panelists will address such issues as (1) How much regularity is needed for adequate yield and cost control?, (2) Will via-programmability make headway against traditional FPGAs?, (3) Are cost and performance gaps between custom and lower-cost fabrics growing or shrinking?, and (4 What are the needs of platform SOC and pure-play foundry constituencies? 22.1 Cheap Submicron: The Next Implementation Fabric Speaker: Andy Broom, - AMI SemiconductorIvo Bolsens, - Xilinx, Inc.Christopher L. Hamlin, - LSI Logic Corp.Zvi Or Bach, - eASIC Corp.Lawrence T. Pileggi, - Carnegie Mellon Univ. Authors: ********************************************************************************** Session: 23 | Title: Testbench, Verification and Debugging: Practical Considerations Time: 10:30 to 12:00 | RM : 210CD Chair: Michael Beaver - iReady Corp., Santa Clara, CA Organizers: Carl Pixley, Rajeev Ranjan This session deals with a hybrid method for formal and simulation based verification using high level abstraction as well as how to compare C programs to RTL. In addition, an effective debugger based upon design exploration is presented. Finally an architecture for mapping a design into emulators is presented to vastly speed up verification. 23.1 Using a Formal Specification and a Model Checker to Monitor and Direct Simulation Verifying the Multiprocessing Hardware of the Alpha 21364 Microprocessor Speaker: Serdar Tasiran, - KOC Univ. Authors:Serdar Tasiran - KOC Univ., Istanabul, Turkey, , Yuan Yu- Microsoft Corp., Mountain View, CA, , Brannon Batson- Intel Corp., Santa Clara, CA 23.2 Advanced Techniques for RTL Debugging Speaker: Bassam Tabbara, - Novas Software, Inc.. Authors:Yu-Chin Hsu, Bassam Tabbara, Yirng-An Chen, , Furshing Tsai, - Novas Software, Inc., San Jose, CA 23.3s Behavioral Consistency of C and Verilog Programs Using Bounded Model Checking Speaker: Daniel Kroening, - Carnegie Mellon Univ. Authors:Daniel Kroening, Edmund Clarke, , Karen Yorav- Carnegie Mellon Univ., Pittsburgh, PA 23.4s Re-use-centric architecture for a fully accelerated testbench environment Speaker: Renate Henftling, - Infineon Tech. Authors:Renate Henftling, Andreas Zinn, Matthias Bauer, Martin Zambaldi, , Wolfgang Ecker, - Infineon Tech., Munich, Germany ********************************************************************************** Session: 24 | Title: Delay and Noise Modeling in the Nanometer Regime Time: 10:30 to 12:00 | RM : 210AB Chair: Vasant Rao - IBM Corp., Hopewell Junction, NY Organizers: Chandu Visweswariah, Narendra V Shenoy Deep sub-micron effects are necessitating the rethinking of delay and noise models for digital circuits. This session describes several novel methods of timing high-performance circuits while taking coupling noise into account. 24.1 An Effective Capacitance Based Driver Output Model for On-Chip RLC Interconnects Speaker: Kanak B. Agarwal, - Univ. of Michigan Authors:Kanak B. Agarwal, Dennis Sylvester, , David Blaauw- Univ. of Michigan, Ann Arbor, MI 24.2s Delay and Slew Metrics Using The Lognormal Distribution Speaker: Charles J. Alpert, - IBM Corp. Authors:Charles J. Alpert, Frank Liu, Chandramouli V. Kashyap, , Anirudh Devgan, - IBM Corp., Austin, TX 24.3s Blade and Razor: Cell and Interconnect Delay Analysis Using Current-Based Models Speaker: John F. Croix, - Silicon Metrics Corp. Authors:John F. Croix - Silicon Metrics Corp., Austin, TX, , Martin D. F. Wong- Univ. of Illinois, Urbana, IL 24.4 Non-Iterative Switching Window Computation for Delay-Noise Speaker: Bhavana Thudi, - Univ. of Michigan Authors:Bhavana Thudi, , David Blaauw- Univ. of Michigan, Ann Arbor, MI ********************************************************************************** Session: 25 | Title: Modeling Issues in the Design of Embedded Systems Time: 10:30 to 12:00 | RM : 209AB Chair: Wolfgang Rosenstiel - Univ. of Tuebingen, Tuebingen, DEU Organizers: Annette Reutter, Donatella Sciuto The session is devoted to the presentation of different performance and communication modelling aspects in the design of embedded systems. The first contribution introduces a performance modelling technique for component based embedded system design. The second paper presents a trace transformation method to perfom communication modelling and refinement of applications. The third paper introduces an approach to optimize performance of programmable heterogeneous multiprocessors through model-based scheduling. The fourth contribution introduces a new shared messaging communication model for efficient inter-task communication in signal processing applications. 25.1 Architecture-Level Performance Evaluation of Component-Based Embedded Systems Speaker: Jeffry T. Russell, - Univ. of Texas Authors:Jeffry T. Russell, , Margarida F. Jacome- Univ. of Texas, Austin, TX 25.2 An IDF-based Trace Transformation Method for Communication Refinement Speaker: Andy D. Pimentel, - Univ. of Amsterdam Authors:Andy D. Pimentel, , Cagkan Erbas- Univ. of Amsterdam, Amsterdam, The Netherlands 25.3s Schedulers as Model-Based Design Elements in Programmable Heterogeneous Multiprocessors Speaker: JoAnn M. Paul, - Carnegie Mellon Univ. Authors:JoAnn M. Paul, Alex Bobrek, Jeffrey E. Nelson, Joshua J. Pieper, , Donald E. Thomas, - Carnegie Mellon Univ., Pittsburgh, PA 25.4s A Complexity Effective Communication Model for Behavioral Modeling of Signal Processing Applications Speaker: Satya Kiran, - Indian Institute of Tech. Authors:Satya Kiran - Indian Institute of Tech., New Delhi, India, , Jayram M.N.- Philips Research Labs., Eindhoven, The Netherlands, Pradeep Rao, , Soumitra K. Nandy, - Indian Institute of Science, Bangalore, India ********************************************************************************** Session: 26 | Title: Special Session: How Application/Technology Evolutions Will Shape Classical EDA? Time: 2:00 to 4:00 | RM : AB Chair: Ahmed Jerraya - TIMA Lab., Grenoble, FRA Organizers: Ahmed A Jerraya SoC design cost threatens the continuation of the current organization of the electronic industry. The number of starting designs is predicted to shrink to 10,000 units/year with 90 nm technology in 2004. Two visions exist at present. The first predicts that this tendency will continue and SoC design starts may go down to 1,000 with 65 nm in 2006 and to only a few dozen with 45 nm in 2008. These will be reconfigurable programmable platforms that will come with specific EDA, like today's FPGA or CPU. The second vision predicts that new trends, like smart SoCs, will maintain the level of new design starts. These will be mixed HW/SW/MEMS designs and will be organized as network-on-chip, but will require generic EDA for network design and component design integration. In both visions, current electronic design methods and existing designers will be hard to scale to accommodate these complex SoCs. The session brings together major semiconductor and system managers and key researchers to explore the two visions. 26.1 Leading-Edge and Future Design Challenges - is the Classical EDA Ready? Speaker: Greg Spirakis, - Intel Corp. Authors:Greg Spirakis - Intel Corp., Santa Clara, CA 26.2 How to Make Efficient Communication, Collaboration, and Optimization from System to Chip Speaker: Akira Matsuzawa, - Tokyo Institute of Tech. Authors:Akira Matsuzawa - Tokyo Institute of Tech., Tokyo 26.3 Extending SoC Life Beyond the Nanometer Wall Speaker: Philippe Magarshak, - STMicroelectronics Authors:Philippe Magarshak - STMicroelectronics, Crolles Cedex, France 26.4 Panel Discussion: Platform Based Design vs. Network on Chip Speaker: Greg Spirakis, - Intel Corp. Authors:Greg Spirakis - Intel Corp., Santa Clara, CA, , Akira Matsuzawa- Tokyo Institute of Tech., Tokyo, , Philippe Magarshak- STMicroelectronics, Crolles Cedex, France, Andrew B. Kahng, - Univ. of California, San Diego, La Jolla, CA, , Alberto L. Sangiovanni-Vincentelli, - Univ. of California, Berkeley, Berkeley, CA, , Giovanni De Micheli, - Stanford Univ., Stanford, CA ********************************************************************************** Session: 27 | Title: SAT and BDD Algorithms for Verification Tools Time: 2:00 to 4:00 | RM : 207ABCD Chair: Robert Damiano - Synopsys Inc., Hillsboro, OR Organizers: Carl Pixley, Hikeung T Ma, Shin-ichi Minato SAT and BDDs are the two most prominent algorithms employed in verification tools today. The first paper of this session mixes SAT, separation logic and unintepreted functions in an efficient way. The second paper defines a new, economical use of BDDs which saves memory. The third paper shows how clever use of circuit structure information can improve the performance of a SAT solver. The fourth paper discusses complete and incomplete methods can be combined to solve the latch mapping problem more efficiently. 27.1 A Hybrid SAT-Based Decision Procedure for Separation Logic with Uninterpreted Functions Speaker: Sanjit A. Seshia, - Carnegie Mellon Univ. Authors:Sanjit A. Seshia, Shuvendu K. Lahiri, , Randal E. Bryant- Carnegie Mellon Univ., Pittsburgh, PA 27.2 Symbolic Representation with Ordered Function Templates Speaker: Amit Goel, - Carnegie Mellon Univ. Authors:Amit Goel - Carnegie Mellon Univ., Pittsburgh, PA, , Gagan Hasteer- Innologic Systems, San Jose, CA, , Randal E. Bryant- Carnegie Mellon Univ., Pittsburgh, PA 27.3 A Signal Correlation Guided ATPG Solver and Its Applications For Solving Difficult Industrial Cases Speaker: Kwang-Ting Cheng, - Univ. of California Authors:Feng Lu, Li C. Wang, , Kwang-Ting Cheng- Univ. of California, Santa Barbara, CAJohn Moondanos, , Ziyad Hanna, - Intel Corp., Hof Carmel, Israel 27.4 Solving the Latch Mapping Problem in an Industrial Setting Speaker: Mukul R. Prasad, - Fujitsu Labs. of America, Inc. Authors:Kelvin Ng - Univ. of British Columbia, Vancouver, BC, Canada, Mukul R. Prasad, Rajarshi Mukherjee, , Jawahar Jain, - Fujitsu Labs. of America, Inc., Sunnyvale, CA ********************************************************************************** Session: 28 | Title: Elements of Functional and Performance Analysis Time: 2:00 to 4:00 | RM : 210CD Chair: Rolf Ernst - Technical Univ. of Braunschweig, Braunschweig, DEU Organizers: Annette Reutter, Margarida Jacome The first paper proposes a formalism capturing key features of transaction level models and an associated set of performance metrics to support design space exploration. The second paper shows how to transform complex process interaction patterns into minimum and maximum arrival curves, thus enabling the use of formal real time analysis techniques. The third paper proposes an automatic approach to check whether simulation traces satisfy functional and performance properties. The fourth paper models the combined effects of speculation, caching and wrong path instruction prefetching to determine the WCET of a program. 28.1 Static Analysis of Transaction-Level Models Speaker: Francesco Bruschi, - Politecnico di Milano Authors:Giovanni Agosta, Francesco Bruschi, , Donatella Sciuto- Politecnico di Milano, Milano, Italy 28.2 Enabling Scheduling Analysis of Heterogeneous Systems with Multi-Rate Data Dependencies and Rate Intervals Speaker: Marek Jersak, - Technical Univ. of Braunschweig Authors:Marek Jersak, , Rolf Ernst- Technical Univ. of Braunschweig, Braunschweig, Germany 28.3 Automatic Trace Analysis for Logic of Constraints Speaker: Xi Chen, - Univ. of California Authors:Xi Chen, , Harry Hsieh- Univ. of California, Riverside, CA, Felice Balarin, , Yosinori Watanabe, - Cadence Berkeley Labs., Berkeley, CA 28.4 Accurate Timing Analysis by Modeling Caches, Speculation and their Interaction Speaker: Abhik Roychoudhury, - National Univ. of Singapore Authors:Xianfeng Li, Tulika Mitra, , Abhik Roychoudhury- National Univ. of Singapore, Singapore, Singapore ********************************************************************************** Session: 29 | Title: Nonlinear Model Order Reduction Time: 2:00 to 4:00 | RM : 210AB Chair: Luca Daniel - Massachusetts Institute of Tech., Cambridge, MA Organizers: Kartikeya Mayaram Nonlinear model order reduction is emerging as a valuable technique for simulation and modeling of analog and MEMS components. The first two papers capture nonlinearities using Volterra series and combine them with Krylov subspace projection methods. The third and fourth papers capture nonlinearities using a trajectory piecewise polynomial and linear approximations combining them with a Krylov subspace projection method and a truncated balance reduction technique respectively. 29.1 NORM: Compact Model Order Reduction of Weakly Nonlinear Systems Speaker: Peng Li, - Carnegie Mellon Univ. Authors:Peng Li, , Lawrence T. Pileggi- Carnegie Mellon Univ., Pittsburgh, PA 29.2 Analog and RF Circuits Macromodels for System-Level Analysis Speaker: Xin Li, - Carnegie Mellon Univ. Authors:Xin Li, Peng Li, Yang Xu, , Lawrence T. Pileggi, - Carnegie Mellon Univ., Pittsburgh, PA 29.3 Piecewise Polynomial Nonlinear Model Reduction Speaker: Ning Dong, - Univ. of Minnesota Authors:Ning Dong, , Jaijeet Roychowdhury- Univ. of Minnesota, Minneapolis, MN 29.4 A TBR-based Trajectory Piecewise-Linear Algorithm for Generating Accurate Low-order Models for Nonlinear Analog Circuits and MEMS Speaker: Dmitry G. Vasilyev, - Massachusetts Institute of Tech. Authors:Dmitry G. Vasilyev, Michal Rewienski, , Jacob White- Massachusetts Institute of Tech., Cambridge, MA ********************************************************************************** Session: 30 | Title: Novel Techniques in High-Level Synthesis Time: 2:00 to 4:00 | RM : 209AB Chair: Christophe Wolinski - Los Alamos National Lab., Los Alamos, NM Organizers: Gila Kamhi, Krzysztof Kuchcinski Higher level synthesis is the eagerly wanted technology but seem to be hard to get. This session brings new hopes with innovative techniques to solve some of the known difficulties of high level synthesis. The first paper innovate by using a static analysis technique, based on smart interval methods from affine arithmetic, to help converting full floating point DSP code into finite-precision format. Two papers explore asynchronous design techniques for high level design. They discuss the efficiency of asynchronous synthesis for processor design. Both papers show promising results. The fourth paper combines space exploration methods from parallelilizing compiler practice with estimates approaches from behavioral synthesis. It shows that this combination is highly effective and efficient for large space exploration. 30.1 Toward Efficient Static Analyis of Finite-Precision Effects in DSP Applications via Affine Arithmetic Modeling Speaker: Claire F. Fang, - Carnegie Mellon Univ. Authors:Claire F. Fang, , Rob A. Rutenbar- Carnegie Mellon Univ., Pittsburgh, PA 30.2 Automating the Design of an Asynchronous DLX Microprocessor Speaker: Ivan Blunno, - Politecnico di Torino Authors:Manish Amde - IIT Bombay, Bombay, India, , Ivan Blunno- Politecnico di Torino, Torino, Italy, , Christos P. Sotiriou- Institute of Computer Science-Forth, Heraklion, Crete., Greece 30.3 High-Level Synthesis of Asynchronous Systems by Data-Driven Decomposition Speaker: Catherine G. Wong, - Caltech Authors:Catherine G. Wong, , Alain J. Martin- Caltech, Pasadena, CA 30.4 Using Estimates from Behavioral Synthesis Tools in Compiler-Directed Design Space Exploration Speaker: Byoungro So, - Univ. of Southern California Authors:Byoungro So, Pedro C. Diniz, , Mary W. Hall- Univ. of Southern California, Marina del Rey, CA ********************************************************************************** Session: 31 | Title: Mixed-Signal Design and Simulation Time: 4:30 to 6:30 | RM : AB Chair: Alan Mantooth - Univ. of Arkansas, Fayetteville, AR Organizers: David Allstot System-on-chip solutions combine analog, digital, RF and MEMS circuits. This session presents emerging analog design and simulation techniques. Two design papers describe a mixed-signal microsystem with integrated MEMS and a fractional-N synthesizer design method. The simulation papers focus on substrate noise, analysis of noise in switched-capacitor circuits and strongly nonlinear symbolic analysis. 31.1 STUDENT DESIGN CONTEST: A 16-Bit Mixed-Signal Microsystem with Integrated CMOS-MEMS Clock Reference Speaker: Robert M. Senger, - Univ. of Michigan Authors:Robert M. Senger, Eric D. Marsman, Michael S. McCorquodale, Fadi H. Gebara, Keith L. KraverMatthew R. Guthaus, , Richard B. Brown, - Univ. of Michigan, Ann Arabor, MI 31.2 Fractional-N Frequency Synthesizer Design at the Transfer Function Level Using a Direct Closed Loop Realization Algorithm Speaker: Charlotte Y. Lau, - Massachusetts Institute of Tech. Authors:Charlotte Y. Lau, , Michael H. Perrott- Massachusetts Institute of Tech., Cambridge, MA 31.3 Characterizing the Effects of Clock Jitter Due to Substrate Noise in Discrete-Time Δ/Σ Modulators Speaker: Payam Heydari, - Univ. of California Authors:Payam Heydari - Univ. of California, Irvine, CA 31.4s Computation of Noise Spectral Density in Switched Capacitor Circuits using the Mixed-Frequency-Time Technique Speaker: Vinita Vasudevan, - Indian Institute of Technology-Madras Authors:Vinita Vasudevan, , Ramakrishna Mokkapati- Indian Institute of Technology-Madras, Chennai, India 31.5s Symbolic Analysis of Analog Circuits with Hard Nonlinearity Speaker: Alicia Manthe, - Univ. of Washington Authors:Alicia Manthe, Zhao Li, , Richard Shi- Univ. of Washington, Seattle, WA ********************************************************************************** Session: 32 | Title: Panel: Nanometer Design: Place Your Bets Time: 4:30 to 6:30 | RM : 207ABCD Chair: Andrew B. Kahng - Univ. of California at San Diego, La Jolla, CA Organizers: In the DAC-2001 debate-panel, "Who's Got Nanometer Design Under Control?", methodologists won the audience vote in a landslide over physics die-hards. Today, physics and economics are much worse than we thought. Yes, methodology can solve any problem, but at what cost? Panelists will prioritize technologies and allocate a fixed R&D budget to address nanometer design challenges. Which problems should get what portion of the budget? What is the likelihood of near-term and long-term success? And who will supply the solutions? 32.1 Nanometer Design: Place Your Bets Speaker: Shekhar Borkar, - Intel Corp.John Cohn, - IBM MicroelectronicsAntun Domic, - Synopsys, Inc.Patrick Groeneveld, - Magma Design Automation, Inc.Louis Scheffer, - Cadence Design Systems, Inc. Authors: ********************************************************************************** Session: 33 | Title: Novel Self-Test Methods Time: 4:30 to 6:30 | RM : 210CD Chair: Janusz Rajski - Mentor Graphics Corp., Wilsonville, OR Organizers: Tim Cheng, TM Mak This session presents new self-test techniques for improving test quality and/or reducing overall test cost. The first paper employs the emerging software-based self-test approach to a modern embedded processor. The second and third papers devise new pattern generation schemes for BIST for higher test quality and lower hardware overhead. The fourth paper present a logic BIST architecture with efficient generation, compression and application of test data. The last paper discusses a low-cost BIST method for linear analog circuits by reusing on-chip resources. 33.1 A Scalable Software-based Self-Test Methodology for Programmable Processors Speaker: Li Chen, - Univ. of California at San Diego Authors:Li Chen - Univ. of California at San Diego, La Jolla, CA, Srivaths Ravi, , Anand Raghunathan- NEC Labs. America, Inc., Princeton, NJ, Sujit Dey, - Univ. of California at San Diego, La Jolla, CA 33.2 A Scan BIST Generation Method using Markov Source and Partial Bit-Fixing Speaker: Wei Li, - Univ. of Iowa Authors:Wei Li, , Chaowen Yu- Univ. of Iowa, Iowa City, IA, , Irith Pomeranz- Purdue Univ., West Lafayette, IN, Sudhakar M. Reddy, - Univ. of Iowa, Iowa City, IA 33.3 Seed Encoding with LFSRs and Cellular Automata Speaker: Ahmad A. Alyamani, - Stanford Univ. Authors:Ahmad A. Alyamani, , Edward J. McCluskey- Stanford Univ., Stanford, CA 33.4s Efficient Compression and Application of Deterministic Patterns in a Logic BIST Architecture Speaker: Peter Wohl, - Synopsys, Inc Authors:Peter Wohl, John A. Waicukauski, Sanjay Patel, , Minesh B. Amin, - Synopsys, Inc, Mountain View, CA 33.5s Ultimate Low Cost Analog BIST Speaker: Marcelo Negreiros, - UFRGS Authors:Marcelo Negreiros, Luigi Carro, , Altamiro A. Susin- UFRGS, Porto Alegre, Brazil ********************************************************************************** Session: 34 | Title: Technology Mapping, Buffering, and Bus Design Time: 4:30 to 6:30 | RM : 210AB Chair: John Lillis - Univ. of Illinois, Chicago, IL Organizers: Charles J Alpert, Dennis Sylvester, Raymond Nijssen This session presents fundamental innovations in buffering and technology mapping. The first paper presents an industrial strength, compreshensive technique for technology mapping using logical effort theory. The second paper examines the van Ginneken's classic buffer insertion algorithm. It presents a sub-quadratic implementation of the classic work. The third paper presents analysis for bi-directional buses that illustrates that midway interleaving of repeaters is not optimium for delay and noise. Analysis leading to an asymmetric positioning is presented. Finally, the session concludes with a paper that uses novel digital filtering techniques to reduce crosstalk in high-speed package-level busses. 34.1 Gain-Based Technology Mapping for Discrete-size Cell Libraries Speaker: Bo Hu, - Univ. of California Authors:Bo Hu - Univ. of California, Santa Barbara, CA, Yosinori Watanabe, , Alex Kondratyev- Cadence Berkeley Labs., Berkeley, CA, Malgorzata Marek-Sadowska, - Univ. of California, Santa Barbara, CA 34.2 An 0(nlogn) Time Algorithm for Optimal Buffer Insertion Speaker: Weiping Shi, - Texas A&M Univ. Authors:Weiping Shi, , Zhuo Li- Texas A&M Univ., College Station, TX 34.3 Optimum Positioning of Interleaved Repeaters in Bidirectional Buses Speaker: Maged M. Ghoneima, - Northwestern Univ. Authors:Maged M. Ghoneima, , Yehea I. Ismail- Northwestern Univ., Evanston, IL 34.4 Synthesizing Optimal Filters for Crosstalk-Cancellation for High-Speed Buses Speaker: Jihong Ren, - Univ. of British Columbia Authors:Jihong Ren, , Mark Greenstreet- Univ. of British Columbia, Vancouver, BC, Canada ********************************************************************************** Session: 35 | Title: Compilation Techniques for Reconfigurable Devices Time: 4:30 to 6:30 | RM : 209AB Chair: Ryan Kastner - Univ. of California, Santa Barbara, CA Organizers: Jens Palsberg, Scott Hauck Reconfigurable systems are driving new approaches to the compilation of hardware systems. This session brings together efforts in compilation and mapping for FPGAs and reconfigurable devices. 35.1 Fast Timing-driven Partitioning-based Placement For Island Style FPGA?s Speaker: Kia Bazargan, - Univ. of Minnesota Authors:Pongstorn Maidee, Cristinel Ababei, , Kia Bazargan- Univ. of Minnesota, Minneapolis, MN 35.2 Global Resource Sharing for Synthesis of Control Data Flow Graphs on FPGAs Speaker: Seda Ogrenci Memik, - Univ. of California Authors:Seda Ogrenci Memik, Gokhan Memik, Roozbeh Jafari, , Eren Kursun, - Univ. of California, Los Angeles, CA 35.3 Compiler-Generated Communication for Pipelined FPGA Applications Speaker: Heidi E. Ziegler, - Univ. of Southern California Authors:Heidi E. Ziegler, Mary Hall, , Pedro Diniz- Univ. of Southern California, Marina Del Rey, CA 35.4 Data Communication Estimation and Reduction for Reconfigurable Systems Speaker: Adam Kaplan, - Univ. of California Authors:Adam Kaplan, Philip Brisk, , Ryan Kastner- Univ. of California, Santa Barbara, CA ********************************************************************************** Session: 36 | Title: Architectural Power Estimation and Optimization Time: 8:30 to 10:00 | RM : AB Chair: Vijay Narayanan - Penn State Univ., University Park, PA Organizers: Chaitali Chakrabarti Papers in this session present different solutions for architectural power estimation and optimization, involving clock-tree power minimization, issue-queue design in high-end microprocessor architectures and on-chip bus interface design. 36.1 Clock-Tree Power Optimization Based on RTL Clock-Gating Speaker: Alessandro Ivaldi, - Politecnico di Torino Authors:Monica Donno, , Alessandro Ivaldi- Politecnico di Torino, Torino, Italy, , Luca Benini- Univ. Di Bologna, Bologna, Italy 36.2 Low-Power Design Methodology for an On-Chip Bus with Adaptive Bandwidth Capability Speaker: Rizwan Bashirullah, - North Carolina State Univ. Authors:Rizwan Bashirullah - North Carolina State Univ., Raleigh, NC, , Wentai Liu- Univ. of California, Santa Cruz, CA, , Ralph K. Cavin- Semiconductor Research Corp., Research Triangle Park, NC 36.3s Power-Aware Issue Queue Design for Speculative Instructions Speaker: Tali Moreshet, - Brown Univ. Authors:Tali Moreshet, , Iris Bahar- Brown Univ., Providence, RI 36.4s State-Based Power Analysis for Systems-on-Chip Speaker: Yunjian W. Jiang, - Univ. of California Authors:Reinaldo A. Bergamaschi - IBM Corp., Yorktown Heights, NY, , Yunjian W. Jiang- Univ. of California, Berkeley, CA ********************************************************************************** Session: 37 | Title: Panel: Libraries: Lifejacket or Straitjacket? Time: 8:30 to 10:00 | RM : 207ABCD Chair: Carl Sechen - Univ. of Washington, Seattle, WA Organizers: Chandu Visweswariah The library abstraction in chip design is breaking down. Three trends are conspiring to necessitate a paradigm shift: performance requirements, low power and SoC integration. The advent of transistor-level options such as multiple threshold voltage choices, multiple oxide thicknesses and transistor sizes (including choices of beta ratios and taper ratios) is causing the sample space for library creation to explode. At the same time, diverse requirements such as ultimate performance, low power, and mixed analog/digital designs in SoCs require intelligent use of all these choices, to say nothing of multiple Vdd choices, high-voltage I/O cells, low-leakage sleep transistors, extremely dense embedded memories including 6T-SRAMs and multi-foundry library offerings. Can sub-micron technologies continue to grow library size? Will we soon have libraries with 10,000 cells? Will tools and characterization methods cope? Will design styles and methodologies be profoundly impacted? Is it the end of libraries as we know them? 37.1 The End of Libraries as We Know Them Speaker: Gregory Northrop, - IBM Corp.Barbara Chappel, - Intel Corp.Andrew Moore, - TSMCJim Hogan, - Artisan Components, Inc.Anjaneya Thakar, - Synopsys, Inc. Authors: ********************************************************************************** Session: 38 | Title: Techniques for Reconfigurable Logic Applications Time: 8:30 to 10:00 | RM : 210CD Chair: Michael Butts - Cadence Design Systems, Inc., Portland, OR Organizers: Majid Sarrafzadeh, Scott Hauck By harnessing the reconfigurable nature of FPGA devices, new high-performance applications are possible, and new techniques are required to utilize these devices. In this session we bring together efforts on high-performance computation, and the precision analysis and fault tolerance techniques necessary to create them. 38.1 Switch-Level Emulation Speaker: Mehdi Baradaran Tahoori, - Stanford Univ. Authors:Ali Reza Ejlali, , Seyed Ghassem Miremadi- Sharif Univ. of Tech., Tehran, Iran 38.2 Designing Fault Tolerant Systems into SRAM-based FPGAs Speaker: Fernanda G. Lima, - UFRGS Authors:Fernanda G. Lima, , Luigi Carro- UFRGS, Porto Alegre, Brazil, , Ricardo L. Reis- Federal Univ. of RGS, Porto Alegre, Brazil 38.3 Determining Appropriate Precisions for Signals in Fixed-Point IIR Filters Speaker: Joan E. Carletta, - Univ. of Akron Authors:Joan E. Carletta, Robert Veillette, Frederick Krach, , Zhengwei Fang, - Univ. of Akron, Akron, OH ********************************************************************************** Session: 39 | Title: Test and Diagnosis for Complex Designs Time: 8:30 to 10:00 | RM : 210AB Chair: Rathish Jayabharathi, - Intel Corp, Folsom, CA Organizers: Seiji Kajihara, TM Mak Designs are certainly getting more complex and not any simpler. Various aspects of testing and diagnosing these complex circuits are highlighted with this 4 papers in this session. The first paper discusses scan patterns application for design that has multiple clock domains. The second paper shows how to improve delay path diagnosis using statistical models. The third paper outlines a method by which internal bus protocols are checked real time with new silicon. Last paper in the session proposes new ways to test FPGA interconnects. 39.1 Test Generation for Designs with Multiple Clocks Speaker: Xijiang Lin, - Mentor Graphics Corp. Authors:Xijiang Lin, , Rob Thompson - Mentor Graphics Corp., Wilsonville, OR 39.2 Enhancing Diagnosis Resolution For Delay Defects Based Upon Statistical Timing and Statistical Fault Models Speaker: Angela Krstic, - Univ. of California Authors:Angela Krstic, Li C. Wang, , Kwang-Ting Cheng- Univ. of California, Santa Barbara, CA, Jing Jia Liou, - National Tsing-Hua Univ., Hsinchu, Taiwan, , T. M. Mak, - Intel Corp., Santa Clara, CA 39.3s Using Embedded Infrastructure IP for SOC Post-Silicon Verification Speaker: Wu-tung Cheng, - Mentor Graphics Corp. Authors:Yu Huang, , Wu-tung Cheng- Mentor Graphics Corp., Wilsonville, OR 39.4s Using Satisfiability in Application Dependent Testing of FPGA Interconnects Speaker: Mehdi Baradaran Tahoori, - Stanford Univ. Authors:Mehdi Baradaran Tahoori - Stanford Univ., Stanford, CA ********************************************************************************** Session: 40 | Title: Special Session: Highlights of ISSCC: High-Speed Heterogenous Design Techniques Time: 8:30 to 10:00 | RM : 209AB Chair: Paul Zuchowski - IBM Microelectronics, Essex Junction, VT Organizers: The first paper describes how to apply the standing wave propagation technique to distribute 10GHz clocks with extremely low skew and jitter. The second paper is devoted to a self-biased PLL with wide multiplication range (1-4096) and extremely low period jitter. The third paper describes the architecture and implementation of a complex signal processing IC. The chip includes an embedded FLASH memory, as well as an embedded dynamically reconfigurable FPGA, usable both to extend the ISA of a micro-processor and as a stand-alone reconfigurable block. 40.1 10 GHz Clock Distribution using Coupled Standing-Wave Oscillators Speaker: Frank O Mahony, - Stanford Univ. Authors:Frank O Mahony - Stanford Univ., Stanford, CA, , C. Patrick Yue- Aeluros, inc., Mountain View, CA, Mark A Horowitz, , S. Simon Wong, - Stanford Univ., Stanford, CA 40.2 Self-Biased High-Bandwidth Low-Jitter 1-to-4096 Multiplier Clock Generator PLL Speaker: John Maneatis, - True Circuits, Inc. Authors:John Maneatis, Jaeha Kim, , Iain McClatchie- True Circuits, Inc., Los Altos, CAJay Maxey, , Manjusha Shankaradas, - Texas Instruments, Inc., Dallas, TX 40.3 A Reconfigurable Signal Processing IC with Embedded FPGA and Multi-Port Flash Memory Speaker: Michele Borgatti, - STMicroelectronics Authors:Michele Borgatti, Lorenzo Cali, Guido De Sandre, Benoit Foret, David IezziFrancesco Lertora, Gilberto Muzzi, Marco Pasotti, Marco Poles, PierLuigi Rolandi ********************************************************************************** Session: 41 | Title: Special Session: Highlights of ISSCC and The Design of State- of- the- Art Microprocessors Time: 10:30 to 12:00 | RM : AB Chair: Noel Menezes - Intel, Hillsboro, OR Organizers: The first paper describes the physical design methodology used to achieve timing closure for a 1.3GHz IBM microprocessor. The second paper focuses on the detection/recovery from the error from noise generated by radiation and other sources and on the clock circuitry design in a 1.3GHz SPARC64 processor. The third paper describes the 1.5GHz Itanium(R) 2 Processor, including details of the 6MB on-die cache design, clock distribution, package, power reduction, database management, timing and reliability verification. 41.1 Physical Synthesis Methodology for High Performance Microprocessors Speaker: Prabhakar Kudva, - IBM Corp. Authors:Yiu Hing Chan, Prabhakar Kudva, Gregory Northrop, Lisa B. Lacey, , Thomas Rosser, - IBM Corp., Austin, TX 41.2 A 1.3GHz Fifth Generation SPARC64 Microprocessor Speaker: Hisashige Ando, - Fujitsu Ltd. Authors:Hisashige Ando, Yuuji Yoshida, Aiichiro Inoue, Isumi Sugiyama, Takeo AsakawaKuniki Morita, Toshiyuki Muta, Tsuyashi Motokurumada, Seishi Okada, Hideo Yamashita, Yoshihiko Satsukawa, Akihiko Konmoto, Ryouichi Yamashita, Hiroyuki Sugiyama 41.3 A 1.5GHz Third Generation Itanium(R) Processor Speaker: Jason Stinson, - Intel Corp. Authors:Jason Stinson, , Stefan Rusu- Intel Corp., Santa Clara, CA ********************************************************************************** Session: 42 | Title: Panel: Formal Verification: Prove it or Pitch it Time: 10:30 to 12:00 | RM : 207ABCD Chair: Rajesh K. Gupta - Univ. of California, San Diego, CA Organizers: As the complexity of chips rides up the Moore's law curve, so does the task of verifying them. Dynamic simulation continues to be critical in this task, but scales poorly. Simulation is time and resource expensive, and so is the cost of crucial bug escapes. For the past few decades, formal verification has held out the most promise. And yet, validation continues to consume most time and effort. Why is this so? Is there relief in sight? Will formal verification eliminate or limit unit level verification and provide the necessary glue for a realistic validation flow? Will the testbenches be replaced by constraints and assertions? Can they be? Can the process be automated? Can validation effort be reused? This panel will explore the issues related to building practical validation flows, and the technologies that the designer community can realistically look forward to materializing in their lifetimes. 42.1 Panel: Formal Verification: Prove it or Pitch it Speaker: Masahiro Fujita, - Tokyo Univ.Fabio Somenzi, - Univ. of ColoradoCarl Pixley, - Synopsys, Inc.Dan Beece, - IBM Corp.John O' Leary, - Intel Corp. Authors: ********************************************************************************** Session: 43 | Title: High Frequency Interconnect Modeling Time: 10:30 to 12:00 | RM : 210CD Chair: Charlie C. P. Chen - Univ. of Wisconsin, Madison, WI Organizers: Bernard N Sheehan, Byron L Krauter This session presents papers in the area of inductance modeling and transmission lines. The first paper presents algorithms used in FastImp, a program for the accurate analysis of wide-band electromagnetic effects in complicated geometries. The next paper develops an inductance extractor based on vector potential equivalent circuits. The third paper presents a design and modeling methodology for high performance transmission line devices. The session is rounded out by a paper on window-based susceptance extraction. 43.1 Algorithms in FastImp: A Fast and Wideband Impedance Extraction Program for Complicated 3-D Geometries Speaker: Zhenhai Zhu, - Massachusetts Institute of Tech. Authors:Zhenhai Zhu, Ben Song, , Jacob White- Massachusetts Institute of Tech., Cambridge, MA 43.2 Vector Potential Equivalent Circuit Based on PEEC Inversion Speaker: Hao Yu, - Univ. of California Authors:Hao Yu, , Lei He- Univ. of California, Los Angeles, CA 43.3s On-chip Interconnect-Aware Design and Modeling Methodology, Based on High Bandwidth Transmission Line Devices Speaker: David Goren, - IBM Haifa Reseach Lab. Authors:David Goren, M. Zelikson, R. Gordin, I. A. Wagner, A. BargerA. Amir, B. Livshitz, , A. Sherman, - IBM Haifa Reseach Lab., Haifa, Israel, R. Groves,J. Park, , Y. Tretiakov, D. Jordan, S. Strang, R. Singh, C. Dickey, D. Harame, - IBM Design Automation Dept., Burlington, US 43.4s An Adaptive Window-Based Susceptance Extraction and its Efficient Implementation Speaker: Guoan Zhong, - Purdue Univ. Authors:Guoan Zhong, Cheng-Kok Koh, Venkataramanan R. Balakrishnan, , Kaushik Roy, - Purdue Univ., West Lafayette, IN ********************************************************************************** Session: 44 | Title: Novel Approaches in Test Cost Reduction Time: 10:30 to 12:00 | RM : 210AB Chair: Yervant Zorian - Virage Logic Corp., Fremont, CA Organizers: Erik Jan Marinissen, Seiji Kajihara Larger ICs make test costs grow. Nanometer technologies require more tests and again make test costs grow. The papers in this session try to tackle these increasing test costs by reducing the test application time and test data volume. 44.1 Test Application Time and Volume Compression through Seed Overlapping Speaker: Alex Orailoglu, - Univ. of California at San Diego Authors:Wenjing Rao - Univ. of California at San Diego, La Jolla, CA, , Ismet Bayraktaroglu- Sun Microsystems, Sunnyvale, CA, , Alex Orailoglu- Univ. of California at San Diego, La Jolla, CA 44.2 Test Cost Reduction for SOCs Using Virtual TAMs and Lagrange Multipliers Speaker: Anuja Sehgal, - Duke Univ. Authors:Anuja Sehgal - Duke Univ., Durham, NC, , Vikram Iyengar- IBM Corp., Essex Jct, VT, Mark D. Krasniewski, , Krishnendu Chakrabarty, - Duke Univ., Durham, NC 44.3s A Cost-Effective Scan Architecture for Scan Testing with Non-Scan Test Power and Test Application Cost Speaker: Dong Xiang, - Tsinghua Univ. Authors:Dong Xiang, , Shan Gu- Tsinghua Univ., Beijing, China, , David Wu- The Chinese Univ. of Hong Kong, Hong Kong, China, Jia-guang Sun, - Tsinghua Univ., Beijing, China 44.4s On Test Data Compression and n-Detection Test Sets Speaker: Sudhakar M. Reddy, - Univ. of iowa Authors:Irith Pomeranz - Purdue Univ., West Lafayette, IN, , Sudhakar M. Reddy- Univ. of Iowa, Iowa City, IA ********************************************************************************** Session: 45 | Title: Retargetable Tools for Embedded Software Time: 10:30 to 12:00 | RM : 209AB Chair: Heinrich Meyr - RWTH, Aachen, DEU Organizers: Anand Raghunathan, Lothar Thiele The complexity of developing and maintaining embedded software tool flows, together with the increasing necessity to port them to new processors, is creating a push towards re-targetability. This session features advances that push the state-of-the-art towards the "holy grail" of re-targetable software tools - performance comparable to (or better than) manually written tools, with seamless re-configurability. The papers in this session focus on micro-architectural simulation, fast instruction-set simulation, and the synthesis of binary decoders that they contain. 45.1 A Retargetable Micro-architecture Simulator Speaker: Wai Sum Mong, - Univ. of Toronto Authors:Wai Sum Mong, , Jianwen Zhu- Univ. of Toronto, Toronto, ON, Canada 45.2 Instruction Set Compiled Simulation: A Technique for Fast and Flexible Instruction Set Simulation Speaker: Mehrdad Reshadi, - Univ. of California Authors:Mehrdad Reshadi, Prabhat Mishra, , Nikil Dutt- Univ. of California, Irvine, CA 45.3 Automated Synthesis of Efficient Binary Decoders for Retargetable Software Toolkits Speaker: Wei Qin, - Princeton Univ. Authors:Wei Qin, , Sharad Malik- Princeton Univ., Princeton, NJ ********************************************************************************** Session: 46 | Title: Special Session: ASIC Design in Nanometer Era - Dead or Alive? Time: 2:00 to 4:00 | RM : AB Chair: Nancy Nettleton - Sun Microsystems, Palo Alto, CA Organizers: Abhijit Dharchoudhury, Sachin S Sapatnekar Cost pressures in nanometer technologies are forcing designers to push the limits of design technology to fully exploit increasingly complex and expensive technology capabilities. ASIC design and libraries must learn to deal with complex design rules, exploit a wide range of features, and contain increasing costs. In this session, the presenters describe the problems and solutions to various facets of mega-ASIC design in the nanometer era. 46.1 Designing Mega-ASICs in Nanotechnology Speaker: David Lackey, - IBM Microelectronics Authors:David Lackey, Juergen Koehl, , Paul Zuchowski- IBM Microelectronics, Essex Junction, VT 46.2 Architecting ASIC Libraries and Flows in Nanometer Era Speaker: Clive Bittlestone, - Texas Instruments, Inc. Authors:Clive Bittlestone, Anthony Hill, Vipul Singhal, , Aravind NV, - Texas Instruments, Inc., Bangalore, India 46.3 Pushing ASIC Performance in a Power Envelope Speaker: Leon Stok, - IBM Corp. Authors:Leon Stok, , Ruchir Puri- IBM Corp., Yorktown Heights, NY, , John Cohn- IBM Microelectronics, Essex Junction, VT, David Kung, - IBM Corp., Yorktown Heights, NY, , Dennis Sylvester, - Univ. of Michigan, Ann Arbor, MI 46.4 Regular Fabrics to Optimize the Performance-Cost Trade-Off Speaker: Lawrence T. Pileggi, - Carnegie Mellon Univ. Authors:Lawrence T. Pileggi, Herman Schmit, , Andrzej Strojwas- Carnegie Mellon Univ., Pittsburgh, PA ********************************************************************************** Session: 47 | Title: Floorplanning and Placement Time: 2:00 to 4:00 | RM : 207ABCD Chair: Carl Sechen - Univ. of Washington, Seattle, WA Organizers: C Y Roger Chen, Ralph Otten Two papers on placement and two papers on floorplanning comprise this session. The first placement paper describes a fast multigrid solver for analytical placement, providing significant speedups over the SOR method. The second paper describes a new clustering approach that takes estimated wire lengths into account, ultimately yielding better placements. The third paper describes a buffer allocation approach that is embedded in the inner loop of a floorplanner, rather than as a post-process, yielding considerably better results. The final paper presents a multi-level floorplanning framework based on a new representation termed MB*-trees. 47.1 An Algebraic Multigrid Solver for Analytical Placement with Layout Based Clustering Speaker: Bo Yao, - Univ. of California at San Diego Authors:Hongyu Chen, , Chung-Kuan Cheng- Univ. of California at San Diego, La Jolla, CA, , Nan-Chi Chou- Mentor Graphics Corp., San Jose, CA, Andrew B. Kahng, - Univ. of California at San Diego, La Jolla, CA, John F. MacDonald, Peter Suaris, - Mentor Graphics Corp., Wilsonville, OR, Bo Yao, , Zhengyong Zhu, - Univ. of California at San Diego, La Jolla, CA 47.2 Wire Length Prediction based Clustering and its Application in Placement Speaker: Bo Hu, - Univ. of California Authors:Bo Hu, , Malgorzata Marek-Sadowska- Univ. of California, Santa Barbara, CA 47.3 Dynamic Global Buffer Planning Optimization Based on Detail Block Locating and Congestion Analysis Speaker: Yuchun Ma, - Tsinghua Univ. Authors:Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, , Yici Cai, - Tsinghua Univ., Beijing, China, , Chung-Kuan Cheng, - Univ. of California at San Diego, La Jolla, CA, , Jun Gu, - HKU of Science and Tech., Hong Kong, China 47.4 Multilevel Floorplanning/Placement for Large-Scale Modules Using B*-Trees Speaker: Yao Wen Chang, - National Taiwan Univ. Authors:Hsun Cheng Lee - Synopsys, Inc., Taipei, Taiwan, , Yao Wen Chang- National Taiwan Univ., Taipei, Taiwan, , Jer Ming Hsu- National Center for High-Performance Computing, Hsinchu, Taiwan, Hannah H. Yang, - Intel Corp., Hillsboro, OR ********************************************************************************** Session: 48 | Title: Advances in SAT Time: 2:00 to 4:00 | RM : 210CD Chair: Per Bjesse - Synopsys, Inc., Hillsboro, OR Organizers: Karem A Sakallah, Rajeev Ranjan SAT technology has become a mainstream technology in design verification. The papers in this session report recent advances that extend the applicability of SAT techniques including -- combining them with BDD based symbolic techniques, enhancing their expressivity by using pseudo-boolean constraints, extending their applicability to unbounded model checking, and leveraging symmetry to prune the search space. 48.1 Checking Satisfiability of a Conjunction of BDDs Speaker: Robert Damiano, - Synopsys, Inc. Authors:Robert Damiano, , James H. Kukula- Synopsys, Inc., Hillsboro, OR 48.2 Learning from BDDs in SAT-based Bounded Model Checking Speaker: Aarti Gupta, - NEC Corp. Authors:Aarti Gupta, , Malay Ganai- NEC Corp., Princeton, NJ, , Chao Wang- Univ. of Colorado, Boulder, COZijiang Yang, , Pranav N. Ashar, - NEC Corp., Princeton, NJ 48.3 A Fast Pseudo-Boolean Constraint Solver Speaker: Donald Chai, - Univ. of California Authors:Donald Chai - Univ. of California, Berkeley, CA, , Andreas Kuehlmann- Cadence Berkeley Labs., Berkeley, CA 48.4s Shatter: Efficient Symmetry-Breaking for Boolean Satisfiability Speaker: Fadi A. Aloul, - Univ. of Michigan Authors:Fadi A. Aloul, Igor L. Markov, , Karem A. Sakallah- Univ. of Michigan, Ann Arbor, MI 48.5s SAT-Based Unbounded Symbolic Model Checking Speaker: Hyeong Ju Kang, - KAIST Authors:Hyeong Ju Kang, , In-Cheol Park- KAIST, Daejeon, Republic of Korea ********************************************************************************** Session: 49 | Title: Novel Design Methodologies and Signal Integrity Time: 2:00 to 4:00 | RM : 210AB Chair: Sharad Mehrotra - Sun Microsystems, Austin, TX Organizers: Abhijit Dharchoudhury, Noel Menezes Interconnect delay dominance and crosscoupling require novel design methodologies and signal integrity techniques to ensure rapid design convergence. The first two papers describe the management of a large ASIC design and a novel way to increase performance in a hierarchical ASIC design methodology, respectively. The third paper discusses the estimation of power grid voltage droops due to statistical leakage current variations. The fourth and fifth papers discuss two topics in noise analysis: the removal of noise pessimism by considering functional relationships and the propagation of noise windows. 49.1 Design of a 17-million Gate Network Processor using a Design Factory Speaker: Gilles Eric Descamps, - Silicon Access Networks Authors:Gilles Eric Descamps, Satish Bagalkotkar, Subramanian Ganesan, Satish Iyengar, , Alain Pirson, - Silicon Access Networks, San Jose, CA 49.2 Hybrid Hierarchical Timing Closure Methodology for a High Performance and Low Power DSP Speaker: Kaijian Shi, - Synopsys, Inc Authors:Kaijian Shi - Synopsys, Inc, Dallas, TX, , Craig Godwin- Texas Instruments, Inc., Dallas, TX 49.3s Statistical Estimation of Leakage-Induced Power Grid Voltage Drop Considering Within-Die Process Variations Speaker: Imad A. Ferzli, - Univ. of Toronto Authors:Imad A. Ferzli, , Farid N. Najm- Univ. of Toronto, Toronto, ON, Canada 49.4s Temporofunctional Crosstalk Noise Analysis Speaker: Alex Kondratyev, - Cadence Berkeley Labs. Authors:Donald Chai - Univ. of California, Berkeley, CA, , Alex Kondratyev- Cadence Berkeley Labs., Berkeley, CA, , Yajun Ran- Univ. of California, Santa Barbara, CA, Kenneth H. Tseng, - Cadence Design Systems, Inc., San Jose, CA, , Yosinori Watanabe, - Cadence Berkeley Labs., Berkeley, CA, , Malgorzata Marek-Sadowska, - Univ. of California, Santa Barbara, CA 49.5 Static Noise Analysis with Noise Windows Speaker: Ken Tseng, - Cadence Design Systems, Inc. Authors:Ken Tseng, , Vinod Kariat- Cadence Design Systems, Inc., San Jose, CA ********************************************************************************** Session: 50 | Title: Memory Optimization for Embedded Systems Time: 2:00 to 4:00 | RM : 209AB Chair: Marcello Lajolo - NEC Corp., Princeton, NJ Organizers: Anand Raghunathan Memory is a bottleneck to achieving higher performance and lower power consumption for many embedded systems. This session presents new approaches to improve the behavior of embedded software by optimizing all parts of the memory sub-system - caches, on-chip memory, and off-chip (DRAM) memory. Presentations will cover topics including smart memories that contain computation capability, optimizing cache behavior through cache architecture and data layout in memory, and techniques to exploit off-chip DRAM access modes. 50.1 Embedded Intelligent SRAM Speaker: Prabhat Jain, - Massachusetts Institute of Tech. Authors:Prabhat Jain, G. Edward Suh, , Srinivas Devadas- Massachusetts Institute of Tech., Cambridge, MA 50.2 Improved Indexing for Cache Miss Reduction in Embedded Systems Speaker: Tony Givargis, - Univ. of California Authors:Tony Givargis - Univ. of California, Irvine, CA 50.3 Memory Layout Technique for Variables Utilizing Efficient DRAM Access Modes in Embedded System Design Speaker: Yoonseo Choi, - KAIST Authors:Yoonseo Choi, , Taewhan Kim- KAIST, Daejon, Republic of Korea 50.4 Interprocedural Optimizations for Improving Data Cache Performance of Array-Intensive Embedded Applications Speaker: Guangyu Chen, - Penn State Univ. Authors:Wei Zhang, Guangyu Chen, , Mahmut Kandemir- Penn State Univ., University Park, PA, Mustafa Karakoy, - Imperial College, London, United Kingdom ********************************************************************************** Session: 51 | Title: Special Session: Design Automation for Quantum Circuits Time: 4:30 to 6:00 | RM : AB Chair: Andreas Kuehlmann - Cadence Berkeley Labs., Berkeley, CA Organizers: Soha Hassoun Modern quantum computing is considered a next frontier in computing. The first paper of this session is an hour-long tutorial that introduces elementary gates for quantum computation, technology-independent quantum logic and quantum design automation. Physical implementation issues and recent experimental results will be discussed. The second paper covers quantum algorithms with an emphasis on small-scale, easily implementable examples and ROM-based computation. The third paper discusses the Quantum Information Science and Technology Roadmapping Project. 51.1 Tutorial: Basic Concepts in Quantum Circuits Speaker: John P. Hayes, - Univ. of Michigan Authors:John P. Hayes - Univ. of Michigan, Ann Arbor, MI 51.2 Designing and Implementing Small Quantum Circuits and Algorithms Speaker: Ben C. Travaglione, - Univ. of Cambridge Computer Lab. Authors:Ben C. Travaglione - Univ. of Cambridge Computer Lab., Cambridge, UK 51.3 A Technology Roadmap for Quantum Computing and Communications Speaker: Richard J. Hughes, - Los Alamos National Lab. Authors:Richard J. Hughes - Los Alamos National Lab., Los Alamos, NM ********************************************************************************** Session: 52 | Title: Energy-Aware System Design Time: 4:30 to 6:00 | RM : 207ABCD Chair: Sujit Dey - Univ. of California at San Diego, La Jolla, CA Organizers: Kaushik Roy, Luca Benini The first two papers of the session are on energy-aware on-chip and off-chip communication system design. The last two papers address practical design and implementaion issues for energy-aware systems for wireless and multi-media applications. 52.1 A Survey of Techniques for Energy Efficient OnChip Communication Speaker: Rajesh K. Gupta, - Univ. of California Authors:Vijay Raghunathan, Mani B. Srivastava, , Rajesh Gupta- Univ. of California, San Diego, CA 52.2 Extending the Lifetime of a Network of Battery-Powered Mobile Devices by Remote Processing: A Markovian Decision-Based Approach Speaker: Peng Rong, - Univ. of Southern California Authors:Peng Rong, , Massoud Pedram- Univ. of Southern California, Los Angeles, CA 52.3s Energy-Aware MPEG-4 FGS Streaming Speaker: Kihwan Choi, - Univ. of Southern California Authors:Kihwan Choi - Univ. of Southern California, Los Angeles, CA, , Kwanho Kim- Seoul National Univ., Seoul, South Korea, , Massoud Pedram- Univ. of Southern California, Los Angeles, CA 52.4s STUDENT DESIGN CONTEST: A Low-Energy Chip-Set for Wireless Intercom Speaker: Michael Sheets, - Univ. of California Authors:Josie Ammer, Michael Sheets, Tufan C. Karalar, Mika Kuulusa, , Jan Rabaey, - Univ. of California, Berkeley, CA ********************************************************************************** Session: 53 | Title: Budgeting, Simulation and Statistical Timing Time: 4:30 to 6:00 | RM : 210CD Chair: Louis Scheffer - Cadence Design Systems, Inc., San Jose, CA Organizers: Kenneth L Shepard, Sudhakar Bobba This session covers various aspects of budgeting, high-level simulation and statistical timing analysis. It begins with a paper on novel delay budgeting using integer programming techniques. The second paper is focused on the principles behind a simulator that obtains the performance of SystemC without sacrificing re-usability. Finally, the third paper describes a path-based statistical static timer that takes all sources of correlations into account. 53.1 Optimal Integer Delay Budgeting on Directed Acyclic Graphs Speaker: Elaheh Bozorgzadeh, - Univ. of California Authors:Elaheh Bozorgzadeh, , Soheil Ghiasi- Univ. of California, Los Angeles, CA, , Atsushi Takahashi- Tokyo Institiute of Tech., Tokyo, Japan, Majid Sarrafzadeh, - Univ. of California, Los Angeles, CA 53.2 Optimizations for a Simulator Construction System Supporting Reusable Components Speaker: David A. Penry, - Princeton Univ. Authors:David A. Penry, , David I. August- Princeton Univ., Princeton, NJ 53.3 Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits Speaker: Chandu Visweswariah, - IBM Corp. Authors:Jochen A. G. Jess - Eindhoven Univ. of Tech., Eindhoven, The Netherlands, , Kerim Kalafala- IBM Corp., Hopewell Junction, NY, Srinath R. Naidu, , Ralph H. J. M. Otten, - Eindhoven Univ. of Tech., Eindhoven, The Netherlands, , Chandu Visweswariah, - IBM Corp, Yorktown Heights, NY ********************************************************************************** Session: 54 | Title: Interconnect Noise Avoidance Methodologies and Slew Rate Prediction Time: 4:30 to 6:00 | RM : 210AB Chair: Sani Nassif - IBM Corp., Austin, TX Organizers: Byron L Krauter, Sachin S Sapatnekar This session is focused on interconnect behavior and noise avoidance. The first paper provides a pragmatic overview of the Pentium 4 interconnect and noise immunity design. The second paper examines the applicability of novel and well known noise reduction techniques in FPGAs. The third paper proposes simple metrics for RC slew rate based on two circuit moments. The final paper provides a methodology for sizing gates taking into account crosstalk. 54.1 Interconnect and Noise Immunity Design for the Pentium 4 Processor Speaker: Rajesh Kumar, - Intel Corp. Authors:Rajesh Kumar - Intel Corp., Portland, OR 54.2 Crosstalk Noise in FPGAs Speaker: Yajun Ran, - Univ. of California Authors:Yajun Ran, , Malgorzata Marek-Sadowska- Univ. of California, Santa Barbara, CA 54.3s Simple Metrics for Slew Rate of RC Circuits Based on Two Circuit Moments Speaker: Kanak B. Agarwal, - Univ. of Michigan Authors:Kanak B. Agarwal, Dennis Sylvester, , David Blaauw- Univ. of Michigan, Ann Arbor, MI 54.4s Post-Route Gate Sizing for Crosstalk Noise Reduction Speaker: Murat R. Becer, - Motorola, Inc. Authors:Murat R. Becer - Motorola, Inc., Austin, TX, , David Blaauw- Univ. of Michigan, Ann Arbor, MI, Ilan Algor, Vladimir Zolotov, Chanhee Oh, Rajendran Panda, - Motorola, Inc., Austin, TX ********************************************************************************** Session: 55 | Title: Analog Design Space Exploration Time: 4:30 to 6:00 | RM : 209AB Chair: Richard Shi - Univ. of Washington, Seattle, WA Organizers: Georges G Gielen Performance space exploration for analog circuits is an important technique for design and synthesis. The papers present novel contributions in this area, including performance trade-off analysis, use of support vector machines and geometric convex modeling. The final paper applies performance space modeling for architectural selection of data converters. 55.1 Performance Trade-off Analysis of Analog Circuits By Normal-Boundary Intersection Speaker: Guido Stehr, - Technical Univ. of Munich Authors:Guido Stehr, Helmut Graeb, , Kurt Antreich- Technical Univ. of Munich, Munich, Germany 55.2 Support Vector Machines for Analog Circuit Performance Representation Speaker: Fernando De Bernardinis, - Univ. of California Authors:Fernando De Bernardinis, Michael Jordan, , Alberto L. Sangiovanni-Vincentelli- Univ. of California, Berkeley, CA 55.3s Efficient Description of the Design Space of Analog Circuits Speaker: Mar Hershenson, - Barcelona Design, Inc. Authors:Mar Hershenson - Barcelona Design, Inc., Newark, CA 55.4s Architectural Selection of A/D Converters Speaker: Martin Vogels, - Katholieke Univ. Authors:Martin Vogels, , Georges G. Gielen- Katholieke Univ., Leuven, Belgium **********************************************************************************