Session: 1 | Title: Panel: CEO PANEL: EDA: This is Serious Business Day: Tuesday June 8 2004 Time: 10:30 to 12:00 | RM : 6A Chair: A. Richard Newton - Univ. of California, Berkeley, CA Organizers: Bob Dahlberg, Kurt Keutzer Over the last 20 years, electronic design has grown to annual revenues of $3B per year and dominates the Technical and Systems Sector of the Software Industry. Cadence and Synopsys are among the top 15 independent software vendors when ranked by market capitalization. In short, the EDA industry has come of age, but the future of the industry is far from certain. Where will the future growth of the industry come from? Are EDA revenues forever tied to the cyclical semiconductor industry? Will there ever be another "next great EDA company" or has the industry settled into a stable tri-opoloy? 1.1 CEO PANEL: EDA: This is Serious Business Speaker: Michael J. Fister, - Cadence Design Systems, Inc.Aart De Geus, - Synopsys, Inc.Walden C. Rhines, - Mentor Graphics Corp. Authors: ********************************************************************************** Session: 2 | Title: Special Session: HOT Leakage Day: Tuesday June 8 2004 Time: 10:30 to 12:00 | RM : 6B Chair: Massoud Pedram - Univ. of Southern California, Los Angeles, CA Organizers: Lei He Leakage has a growing importance due to technology scaling, and for better control thermal dependency must be considered to better control leakage. This session surveys state-of-the-art leakage reduction at device, circuit and system levels, and poses challenges and opportunities for further CAD development. 2.1 Circuit and Device Optimizations with Electrothermal Coupling in Scaled Technologies Speaker: Ali Keshavarzi, - Intel Corp. Authors:Arman Vassighi, , Ali Keshavarzi- Intel Corp, Hillsboro, OR, Siva Narendra, Seri Lee, Yibin Ye, Vivek De, - Intel Corp., Hillsboro, OR 2.2 Leakage Estimation and Leakage Control for Nano-Scale CMOS Circuits Speaker: Kaushik Roy, - Purdue Univ. Authors:Kaushik Roy - Purdue Univ., West Lafayette, IN, , Saibal Mukhopadhyay- Univ. Waterloo, Waterloo, ON, Canada 2.3 System Level Leakage Reduction Considering the Interdependency between Temperature and Leakage Speaker: Lei He, - Univ. of California Authors:Lei He, , Weiping Liao- Univ. of California, Los Angeles, CA, , Mircea R. Stan- Univ. of Virginia, Charlottesville, VA ********************************************************************************** Session: 3 | Title: Clock Routing and Buffering Day: Tuesday June 8 2004 Time: 10:30 to 12:00 | RM : 6C Chair: John Lillis - Univ. of Illinois, Chicago, IL Organizers: Dirk Stroobandt, Raymond Nijssen This session presents three papers on clock routing and buffering that address critical design challenges in today's deep sub-micron regime. The first paper shows how to add cross links to current clock tree routing constructions to reduce variability. The next paper presents a fast buffering technique that can handle a variety of physical environment constraints. The last paper in the session presents a method for choosing repeaters that minimize power while maintaining excellent daley characteristics, which is becoming an increasingly prevalent problem. 3.1 Reducing Clock Skew Variability via Cross Links Speaker: Anand Rajaram, - Texas A&M Univ. Authors:Anand Rajaram, Jiang Hu, , Rabi Mahapatra- Texas A&M Univ., College Station, TX 3.2 Fast and Flexible Buffer Trees That Navigate the Physical Layout Environment Speaker: Milos Hrkic, - Univ. of Illinois Authors:Charles J. Alpert - IBM Corp., Austin, TX, , Milos Hrkic- Univ. of Illinois, Chicago, IL, , Jiang Hu- Texas A&M Univ., College Station, TX, Stephen T. Quay, - IBM Corp., Austin, TX 3.3 Practical Repeater Insertion For Low Power: What Repeater Library Do We Need? Speaker: Xun Liu, - North Carolina State Univ. Authors:Xun Liu, , Yuantao Peng- North Carolina State Univ., Raleigh, NC, , Marios C. Papaefthymiou- Univ. of Michigan, Ann Arbor, MI ********************************************************************************** Session: 4 | Title: Tools and Strategies for Dynamic Verification Day: Tuesday June 8 2004 Time: 10:30 to 12:00 | RM : 6D Chair: Jacob Abraham - Univ. of Texas, Austin, TX Organizers: Adnan Aziz, Yaron Kashi Successful dynamic verification is built upon several closely linked concepts. This session addresses a number of these concepts: recent advances in test generation targeting processors, tools for measuring and analyzing functional coverage, and a regression strategy optimized for coverage. 4.1 Industrial Experience with Test Generation Languages for Processor Verification Speaker: Michael Vinov, - IBM Corp. Authors:Michael Behm, Yossi Lichtenstein, John Ludden, Michal Rimon, , Michael Vinov, - IBM Corp., Haifa, Israel 4.2s Defining Coverage Views to Improve Functional Coverage Analysis Speaker: Eitan Marcus, - IBM Corp. Authors:Sigal Asaf, Eitan Marcus, , Avi Ziv- IBM Corp., Haifa, Israel 4.3s Systematic Functional Coverage Metric Synthesis from Hierarchical Temporal Event Relation Graph Speaker: Young-Su Kwon, - KAIST Authors:Young-Su Kwon, Young-IL Kim, , Chong-Min Kyung- KAIST, Daejeon, Republic of Korea 4.4 Probabilistic Regression Suites for Functional Verification Speaker: Avi Ziv, - IBM Corp. Authors:Shai Fine, Shmuel Ur, , Avi Ziv- IBM Corp., Haifa, Israel ********************************************************************************** Session: 5 | Title: Timing-Driven System Synthesis Day: Tuesday June 8 2004 Time: 10:30 to 12:00 | RM : 4 Chair: Prashant Sawkar - Intel Corp., Hillsboro, OR Organizers: Gila Kamhi, Krzysztof Kuchcinski This session includes papers discussing different approaches to timing-driven modular design. Results are provided on scalable system level design with tight connections to physical level timing requirements. The first two papers promote scalable and hierarchical design methodology through modular scheduling and formal synthesis of timing optimised scheduling algorithms. The last two papers discuss timing problems at the system level in connection to physical design. Their approaches address the problem of handling system level long wire delays encountered at later design stages. 5.1 Modular Scheduling of Guarded Atomic Actions Speaker: Daniel L. Rosenband, - Massachusetts Institute of Tech.Arvind, - Massachusetts Institute of Tech. Authors:Daniel L. Rosenband, , Arvind- Massachusetts Institute of Tech., Cambridge, MA 5.2 Automatic Correct Scheduling of Control Flow Intensive Behavioral Descriptions in Formal Synthesis Speaker: Kai Kapp, - Univ. of Karlsruhe Authors:Kai Kapp, , Viktor Sabelfeld- Univ. of Karlsruhe, Karlsruhe, Germany 5.3s A Timing-Driven Chip-Level Design Flow Speaker: Fan Mo, - Univ. of California Authors:Fan Mo, , Robert K. Brayton- Univ. of California, Berkeley, CA 5.4s Timing Closure through a Globally Synchronous Timing Partitioned Design Methodology Speaker: Christer Svensson, - Linkoping Univ. Authors:Anders Edman, , Christer Svensson- Linkoping Univ., Linkoping, Sweden ********************************************************************************** Session: 6 | Title: Special Session: Reliable System-on-a-Chip Design in the Nanometer Era Day: Tuesday June 8 2004 Time: 2:00 to 4:00 | RM : 6A Chair: Chandu Visweswariah - IBM, Corp, Yorktown Heights, NY Organizers: Naresh Shanbhag,Giovanni De Micheli Reliability of systems-on-chips (SOCs) is recognized to be the major problem of this decade. In addition to performance and power dissipation, SOCs also have to satisfy constraints on mean time to failure. The dramatic increase in complexity further compounds the problem. This special session will focus on the reliability problem in SOCs at the semiconductor process technology, algorithms, computation, communication, systems and software levels. These presentations will be coordinated to provide a comprehensive view of this important problem. 6.1 Design and Reliability Challenges in Nanometer Technologies Speaker: Shekhar Borkar, - Intel Corp. Authors:Shekhar Borkar, Tanay Karnik, , Vivek De- Intel Corp., Hillsboro, OR 6.2s A Communication-Theoretic Design Paradigm for Reliable SoCs Speaker: Naresh Shanbhag, - Univ. of Illinois, Urbana-Champaign Authors:Naresh Shanbhag - Univ. of Illinois, Urbana, IL 6.3s Reliable Communication in SoCs Speaker: Giovanni De Micheli, - Stanford Univ. Authors:Giovanni De Micheli - Stanford Univ., Stanford, CA 6.4s Designing Robust Microarchitectures Speaker: Todd Austin, - Univ. of Michigan Authors:Todd Austin - Univ. of Michigan, Ann Arbor, MI 6.5s Hierarchical Application-Aware Error Detection and Recovery Speaker: Zbigniew Kalbarczyk, - Univ. of Illinois Authors:Ravishankar K. Iyer - Univ. of Illinois, Urbana, IL 6.6 Panel Discussion Speaker: Authors: ********************************************************************************** Session: 7 | Title: Panel: When IC Yield Missed the Target, Who is at Fault? Day: Tuesday June 8 2004 Time: 2:00 to 4:00 | RM : 6B Chair: Lucio Lanza - Lanza techVentures, Palo Alto, CA Organizers: Andrzej Strojwas Silicon yield once was dominated by contaminants and particulates, making yield a process issue. But with today's electronics supply chain, multiple suspects may be indicted on manufacturability issues. Who is responsible for preventive actions in manufacturability and yield? The panelists, representing a foundry, a fabless company, an IP provider, two EDA vendors, and an IC design team, will discuss the problems and solutions for achieving manufacturability and yield goals. 7.1 When IC yield misses the target, who is at fault? Speaker: Michael Campbell, - QualCommVassilios C. Gerousis, - Infineon TechJohn Kibarian, - PDF Solutions, IncJim Hogan, - Telos Venture PartnersMarc Levitt, - Cadence Design Systems, Inc. Authors: ********************************************************************************** Session: 8 | Title: Power Modeling and Optimization for Embedded Systems Day: Tuesday June 8 2004 Time: 2:00 to 4:00 | RM : 6C Chair: Massoud Pedram - Univ. of Southern California, Los Angeles, CA Organizers: Luca Benini, Trevor Mudge Embedded system designers critically need high-level models for software and harware. This session includes contributions on advanced modeling and optimization approaches for critical system-level components, namely: on-chip interconnect, memory system, high speed io links and software. 8.1 Memory Access Scheduling and Binding Considering Energy Minimization in Multi-Bank Memory Systems Speaker: Chun-Gi Lyuh, - ETRI Authors:Chun-Gi Lyuh - ETRI, Daejeon, Republic of Korea, , Taewhan Kim- Seoul National Univ., Seoul, Republic of Korea 8.2 Profile-Based Optimal Intra-Task Voltage Scheduling for Hard Real-Time Applications Speaker: Jaewon Seo, - KAIST Authors:Jaewon Seo - KAIST, Daejeon, Republic of Korea, , Taewhan Kim- Seoul National Univ., Seoul, Republic of Korea, , Ki-Seok Chung- Hanyang Univ., Seoul, Republic of Korea 8.3 Requirement-Based Design Methods for Adaptive Communications Links Speaker: Juan Antonio Carballo, - IBM Corp. Authors:Juan Antonio Carballo, Kevin Nowka, Seung-Moon Yoo, Ivan Vo, Robert Norman, Clay Cranford, - IBM Corp., Raleigh, NC 8.4s Automated Energy/Performance Macromodeling of Embedded Software Speaker: Anish Muttreja, - Princeton Univ. Authors:Anish Muttreja - Princeton Univ., Princeton, NJ, Anand Raghunathan, , Srivaths Ravi- NEC Labs., Princeton, NJ, Niraj K. Jha, - Princeton Univ., Princeton, NJ 8.5s Coding for System-on-Chip Networks: A Unified Framework Speaker: Srinivasa R. Sridhara, - Univ. of Illinois Authors:Srinivasa R. Sridhara, , Naresh R. Shanbhag- Univ. of Illinois, Urbana, IL ********************************************************************************** Session: 9 | Title: Performance Evaluation and Run Time Support Day: Tuesday June 8 2004 Time: 2:00 to 4:00 | RM : 6D Chair: Joerg Henkel - Univ. of Karlsruhe, Karlsruhe, Germany Organizers: Radu Marculescu, Rainer Leupers Evaluating system performance is a critical issue in systems design. Of particular interest is performance evaluation at higher levels of abstraction. The papers in this session cover techniques ranging from WCET to run-time support for various architectures and platforms. The first two papers deal with early performance estimation. The next two propose new optimization techniques for dynamic scheduling. Finally, the last paper presents an area estimation technique for reconfigurable devices. 9.1 Abstraction of Assembler Programs for Symbolic Worst Case Execution Time Analysis Speaker: Tobias Schuele, - Univ. of Kaiserslautern Authors:Tobias Schuele, , Klaus Schneider- Univ. of Kaiserslautern, Kaiserslautern, Germany 9.2 Extending the Transaction Level Modeling Approach for Fast Communication Architecture Exploration Speaker: Sudeep Pasricha, - Univ. of California Authors:Sudeep Pasricha, , Nikil Dutt- Univ. of California, Irvine, CA, , Mohamed Ben-Romdhane- Conexant Systems, Inc., Newport Beach, CA 9.3 Specific Scheduling Support to Minimize the Reconfiguration Overhead of Dynamically Reconfigurable Hardware Speaker: David Atienza, - Univ. Complutense de Madrid Authors:Javier Resano - Univ. Complutense de Madrid, Madrid, Spain, , Diederik Verkest- IMEC, Leuven, Belgium, , Daniel Mozos- Univ. Complutense de Madrid, Madrid, SpainFrancky Catthoor, , Serge Vernalde, - IMEC, Leuven, Belgium 9.4s LODS: Locality-Oriented Dynamic Scheduling for On-Chip Multiprocessors Speaker: Mahmut Kandemir, - Penn State Univ. Authors:Mahmut Kandemir - Penn State Univ., University Park, PA 9.5s An Area Estimation Methodology for FPGA Based Designs at System-C Level Speaker: Carlo Brandolese, - Politecnico di Milano Authors:Carlo Brandolese, Fabio Salice, , William Fornaciari- Politecnico di Milano, Milano, Italy ********************************************************************************** Session: 10 | Title: Advances in Analog Circuit and Layout Synthesis Day: Tuesday June 8 2004 Time: 2:00 to 4:00 | RM : 4 Chair: Koen Lampaert - Mindspeed Technologies, Inc., Newport Beach, CA Organizers: Georges G. Gielen, Koen Lampaert This session deals with important advances in analog circuit and layout synthesis. The first paper presents a method for designing operational amplifiers using reversed geometric programming. The next paper describes an analog layout-centric reuse strategy. The third paper proposes techniques for fast estimation of parasitics during layout synthesis. Synthesis of reconfigurable analog circuits is described next. The session ends with a presentation on an electrical and physical synthesis flow for radio frequency integrated circuits. 10.1 Automated Design of Operational Transconductance Amplifiers Using Reversed Geometric Programming Speaker: Johan P. Vanderhaegen, - Univ. of California Authors:Johan P. Vanderhaegen, , Robert W. Brodersen- Univ. of California, Berkeley, CA 10.2 Correct-by-Construction Layout-Centric Retargeting of Large Analog Designs Speaker: Sambuddha Bhattacharya, - Univ. of Washington Authors:Sambuddha Bhattacharya, Nuttorn Jangkrajarng, Roy Hartono, , Richard Shi, - Univ. of Washington, Seattle, WA 10.3 Fast and Accurate Parasitic Capacitance Models for Layout-Aware Synthesis of Analog Circuits Speaker: Anuradha Agarwal, - Univ. of Cincinnati Authors:Anuradha Agarwal - Univ. of Cincinnati, Cincinnati, OH, , Hemanth Sampath- Univ. of Cinicinnati, Cincinnati, OH, Veena Yelamanchili, , Ranga Vemuri, - Univ. of Cincinnati, Cincinnati, OH 10.4s ORACLE: Optimization with Recourse of Analog Circuits Including Layout Extraction Speaker: Lawrence T. Pileggi, - Carnegie Mellon Univ. Authors:Yang Xu, , Lawrence T. Pileggi- Carnegie Mellon Univ., Pittsburgh, PA, , Stephen P. Boyd- Stanford Univ., Stanford, CA 10.5s A Synthesis Flow Toward Fast Parasitic Closure for Radio-Frequency Integrated Circuits Speaker: Gang Zhang, - Carnegie Mellon Univ. Authors:Gang Zhang - Carnegie Mellon Univ., Pittsburgh, PA, Aykut Dengi, , Ronald A. Rohrer- Neolinear, Inc., Pittsburgh, PA, Rob A. Rutenbar, - Carnegie Mellon Univ., Pittsburgh, PA, , L. Richard Carley, - Carnegie Mellon Unive., Pittsburgh, PA ********************************************************************************** Session: 11 | Title: Power Grid Design and Analysis Techniques Day: Tuesday June 8 2004 Time: 4:30 to 6:30 | RM : 6A Chair: Eli Chiprout - Intel Corp., Chandler, AZ Organizers: Abhijit Dharchoudhury, Lei He This session deals with power grid and clock design and analysis. The first paper considers buffer sizing for low power with clock skew constraints. The second paper discusses optimal placement of power pads and pins. The third paper proposes a stochastic approach to P/G analysis and the fourth paper describes a practical application of macro-modeling to P/G analysis. The last paper presents a layout decompaction technique to correct EM failures. 11.1 Buffer Sizing for Clock Power Minimization Subject to General Skew Constraints Speaker: Kai Wang, - Univ. of California at Santa Barbara Authors:Kai Wang, , Malgorzata Marek-Sadowska- Univ. of California, Santa Barbara, CA 11.2 Optimal Placement of Power Supply Pads and Pins Speaker: Min Zhao, - Freescale Semiconductor, Inc. Authors:Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, , Rajendran Panda, - Motorola, Inc., Austin, TX 11.3 A Stochastic Approach to Power Grid Analysis Speaker: Sanjay Pant, - Univ. of Michigan Authors:Sanjay Pant, , David Blaauw- Univ. of Michigan, Ann Arbor, MI, Vladimir Zolotov, Savithri Sundareswaran, , Rajendran Panda, - Motorola, Inc., Austin, TX 11.4s Efficient Power/Ground Network Analysis for Power Integrity-Driven Design Methodology Speaker: Su-Wei Wu, - Elan Microelectronics Corp. Authors:Su-Wei Wu - Elan Microelectronics Corp., Hsinchu, Taiwan, , Yao Wen Chang- National Taiwan Univ., Taipei, Taiwan 11.5s Reliability-Driven Layout Decompaction for Electromigration Failure Avoidance in Complex Mixed-Signal IC-Designs Speaker: Goeran Jerke, - Robert Bosch GmbH Authors:Goeran Jerke - Robert Bosch GmbH, Reutlingen, Germany, , Jens Lienig- Dresden Univ. of Tech., Dresden, Germany, , Juergen Scheible- Robert Bosch GmbH, Reutlingen, Germany ********************************************************************************** Session: 12 | Title: Panel: What Happened to ASIC? Go (Recon)figure? Day: Tuesday June 8 2004 Time: 4:30 to 6:30 | RM : 6B Chair: Kurt Keutzer - Univ. of California, Berkeley, CA Organizers: Nitin Deo, Behrooz Zahiri Increasing design cost and risk is causing more and more designers to build configurable platforms that will amortize design and manufacturing costs across many generations. Several reconfiguration schemes exist and none of them seems to be a clear winner. Most notably there are three forms of technology: structured ASIC, configurable software programmable, reconfigurable FPGA-like platform. New solutions are emerging and may induce drastic changes in the current industry organization. The panel will examine factors in the success of the various options, and look to what the future might bring. 12.1 What Happened to ASIC? Go (Recon)figure? Speaker: Phillip LoPresti, - NEC Electronics AmericaRay Simar, - Texas Instruments, Inc.Chris Rowen, - Tensilica, Inc.Michele Borgatti, - STMicroelectronicsChris Reynolds, - IBM Corp. Authors: ********************************************************************************** Session: 13 | Title: Methods for a Priori Feasible Layout Generation Day: Tuesday June 8 2004 Time: 4:30 to 6:30 | RM : 6C Chair: K. S. (Hardy) Leung - Magma Design Automation, Inc., Santa Clara, CA Organizers: Charles J. Alpert, Dirk Stroobandt, Raymond Nijssen This session combines methods that demonstrate the effectiveness of a priori-correct layout generation. The first paper addresses this by modeling the effects of modern lithography so as to avoid routing patterns complicating optical proximity correction. The following three papers focus on a topic of great interest: regular fabrics for improved manufacturing yield and cost. These papers successfully narrow the flexibility gap between regular and structured ASICs. The final paper discusses improved layout predictability through more accurate pre-layout standard cell characterization. 13.1 Optical Proximity Correction (OPC)-Friendly Maze Routing Speaker: Li-Da Huang, - Univ. of Texas Authors:Li-Da Huang - Univ. of Texas, Austin, TX, , Martin D.F. Wong- Univ. of Illinois, Urbana-Champaign, IL 13.2 Design Automation for Mask Programmable Fabrics Speaker: Narendra V. Shenoy, - Synopsys, Inc. Authors:Narendra V. Shenoy, Jamil Kawa, , Raul Camposano- Synopsys, Inc, Mountain View, CA 13.3 On Designing Via-Configurable Cell Blocks for Regular Fabrics Speaker: Yajun Ran, - Univ. of California Authors:Yajun Ran, , Malgorzata Marek-Sadowska- Univ. of California, Santa Barbara, CA 13.4s Routing Architecture Exploration for Regular Fabrics Speaker: Veerbhan Kheterpal, - Carnegie Mellon Univ. Authors:Veerbhan Kheterpal - Carnegie Mellon Univ., Pittsburgh, PA 13.5s Accurate Estimation of Standard Cell Characteristics Speaker: Hiroaki Yoshida, - Zenasis Technologies, Inc. Authors:Hiroaki Yoshida, Kaushik De, , Vamsi Boppana- Zenasis Technologies, Inc., Campbell, CA ********************************************************************************** Session: 14 | Title: Abstraction Techniques for Functional Verification Day: Tuesday June 8 2004 Time: 4:30 to 6:30 | RM : 6D Chair: Vigyan Singhal - Jasper Design Automation, Mountain View, CA Organizers: Karem A. Sakallah, Rajeev Ranjan Abstraction techniques are essential for improving the capacity and performance of formal functional verification tools. The first paper combines bit-level SAT and word-level ILP solvers to verify both the control and datapath of RTL designs. The second paper performs automatic uninterpreted function abstraction of Verilog models to establish functional equivalence between an RTL design and its specification. The third paper enhances state-of-the-art abstraction refinement techniques by using two novel metrics. The last two papers describe case studies which demonstrate how real world designs can be effectively verified using formal methods. 14.1 An Efficient Finite Domain Constraint Solver for Circuits Speaker: Ganapathy Parthasarathy, - Univ. of California Authors:Ganapathy Parthasarathy, Madhu K. Iyer, Kwang T. Cheng, , Li C. Wang, - Univ. of California, Santa Barbara, CA 14.2 Automatic Abstraction and Verification of Verilog Models Speaker: Zaher S. Andraus, - Univ. of Michigan Authors:Zaher S. Andraus, , Karem A. Sakallah- Univ. of Michigan, Ann Arbor, MI 14.3 Abstraction Refinement by Controllability and Cooperativeness Analysis Speaker: Freddy Y.C. Mang, - Synopsys, Inc. Authors:Freddy Y. C. Mang, , Pei-Hsin Ho- Synopsys, Inc., Portland, OR 14.4s Verifying a Gigabit Ethernet Switch Using SMV Speaker: Yuan Lu, - Broadcom Corp. Authors:Yuan Lu, , Mike Jorda- Broadcom Corp., San Jose, CA 14.5s A General Decomposition Strategy for Verifying Register Renaming Speaker: Mark D. Aagaard, - Univ. of Waterloo Authors:Hazem I. Shehata, , Mark D. Aagaard- Univ. of Waterloo, Waterloo, ON, Canada ********************************************************************************** Session: 15 | Title: Memory and Network Optimization in Embedded Designs Day: Tuesday June 8 2004 Time: 4:30 to 6:30 | RM : 4 Chair: Faraydon Karim - STMicroelectronics, La Jolla, CA Organizers: Adam Donlin, Grant E. Martin Generic methods for designing memory and communications architectures for embedded applications are completely insufficient for modern design. This session presents advanced results in new approaches to optimizing memory and network architectures. The first two papers cover run-time scratchpad structures and code compression. The next one links the themes of memory subsystem and on-chip networks together for multi-processor SoC. The final two short papers cover particular aspects of NoC design: moving OS functions for NoC to hardware and designing new hybrid routing algorithms to optimize on-chip communication. 15.1 An Integrated Hardware Software Approach for Run-Time Scratchpad-Management Speaker: Francesco Poletti, - Univ. Di Bologna Authors:Francesco Poletti - Univ. Di Bologna, Bologna, Italy, , Paul Marchal- IMEC, Leuven, Belgium, , David Atienza- DACYA/UCM, Madrid, Spain, Luca Benini, - Univ. di Bologna, Bologna, Italy, , Francky Catthoor, - IMEC, Leuven, Belgium, , Jose Mendias, - DACYA/UCM, Madrid, Spain 15.2 Multi-Profile Based Code Compression Speaker: Eduardo B. Wanderleynetto, - CEFETRN/IC-UNICAMP Authors:Eduardo B. Wanderleynetto, Rodolfo J. Azevedo, Paulo C. Centoducatte, , Guido S. Araujo, - IC-UNICAMP, Campinas, Brazil 15.3 An Efficient Scalable and Flexible Data Transfer Architecture for Multiprocessor SoC with Massive Distributed Memory Speaker: Marius Petru Bonaciu, - TIMA Lab. Authors:Sang Il Han - Seoul National Univ., Seoul, Republc of Korea, , Amer Baghdadi- ENST Bretagne, Brest, France, , Marius Petru Bonaciu- TIMA Lab., Grenoble, France, Soo Ik Chae, - Seoul National Univ., Seoul, Republic of Korea, , Ahmed Amine Jerraya, - TIMA Lab., Grenoble, France 15.4s Operating-System Controlled Network on Chip Speaker: Vincent Nollet, - IMEC Authors:Vincent Nollet, Theodore M. Marescaux, Diederik Verkest, Jean-Yves Mignolet, , Serge Vernalde, - IMEC, Leuven, Belgium 15.5s DyAD - Smart Routing for Networks-on-Chip Speaker: Jingcao Hu, - Carnegie Mellon Univ. Authors:Jingcao Hu, , Radu Marculescu- Carnegie Mellon Univ., Pittsburgh, PA ********************************************************************************** Session: 16 | Title: Special Session: The Future of Timing Closure Day: Wednesday June 9 2004 Time: 8:30 to 10:00 | RM : 6A Chair: Phiroze Parakh - Sierra Design Automation, Inc., Santa Clara, CA Organizers: Charles J. Alpert Timing closure is far from solved, and approaches are diverging. Leading-edge methodologies cope with variability, leakage, and wiring predictability, while new “platform tools” aim for chip-level optimization, and academic research offers the promise of “single-pass” closure at long last. 16.1 Timing Closure for Low-FO4 Microprocessor Design Speaker: David S. Kung, - IBM Corp. Authors:David S. Kung - IBM Corp., Yorktown Heights, NY 16.2 Forest vs. Trees: Where's the Slack? Speaker: Paul Rodman, - ReShape, Inc. Authors:Paul Rodman - ReShape, Inc., Mountain View, CA 16.3 Efficient Timing Closure Without Timing Driven Placement and Routing Speaker: Carl Sechen, - Univ. of Washington Authors:Miodrag Vujkovic, , David Wadkins- Univ. of Washington, Seattle, WA, , William Swartz- InternetCAD.com, Inc., Dallas, TX, Carl Sechen, - Univ. of Washington, Seattle, WA ********************************************************************************** Session: 17 | Title: Panel: Verification, What Works and What Doesn't Day: Wednesday June 9 2004 Time: 8:30 to 10:00 | RM : 6B Chair: Robert Damiano - Synopsys, Inc., Hillsboro, OR Organizers: Francine Bacchini Today’s leading chip and system companies are faced with ever increasing design verification challenges; industry studies revealing that as much as 50% of the total schedule is being spent in verification. Large companies, with almost infinite resources, have shown that throwing CPU cycles and people at the simulation problem still doesn’t guarantee a level of coverage desired by the design team. So, what is the answer? Are assertions, faster simulators, and testbench languages the "holy grail", or are those just micro-optimizations of a methodology that is fundamentally flawed? Is there hope for a verification methodology that completely covers a design with a predictable verification schedule? The panelists will describe their experiences of what works, and what doesn’t, providing insights into their methodologies and philosophies. 17.1 Verification, What Works and What Doesn't Speaker: Bob Bentley, - Intel Corp.Makoto Ishii, - Sony Corp.Einat Yogev, - Cisco Systems, Inc.Kurt Baty, - WSFDB ConsultingKevin Normoyle, - Azul Systems, Inc. Authors: ********************************************************************************** Session: 18 | Title: Design Space Exploration and Scheduling for Embedded Software Day: Wednesday June 9 2004 Time: 8:30 to 10:00 | RM : 6C Chair: Mahmut Kandemir - Penn State Univ., University Park, PA Organizers: Heinrich Meyr, Lothar Thiele, Mahmut Kandemir Future embedded systems have to deal with increasing heterogeneity on the one hand and influence from physical implementation on the other hand to achieve the required performance in an energy efficient way. In this session we address the exploration from both caches and the system level view point. In addition, power constraints under the current constraints of leakage are discussed. 18.1 Leakage Aware Dynamic Voltage Scaling for Real-Time Embedded Systems Speaker: Ravindra Jejurikar, - Univ. of California Authors:Ravindra Jejurikar - Univ. of California, Irvine, CA, Cristiano Pereira, , Rajesh Gupta- Univ. of California at San Diego, La Jolla, CA 18.2 Retargetable Profiling for Rapid, Early System Level Design Space Exploration Speaker: Lukai Cai, - Univ. of California Authors:Lukai Cai, Andreas Gerstlauer, , Daniel Gajski- Univ. of California, Irvine, CA 18.3 High Level Cache Simulation for Heterogeneous Multiprocessors Speaker: Joshua J. Pieper, - Carnegie Mellon Univ. Authors:Joshua J. Pieper - Carnegie Mellon Univ., Pittsburgh, PA, , Alain Mellan- STMicroelectronics, San Diego, CA, Joann M. Paul, , Donald E. Thomas, - Carnegie Mellon Univ., Pittsburgh, PA, , Faraydon Karim, - STMicroelectronics, San Diego, CA ********************************************************************************** Session: 19 | Title: Advances in Accelerated Simulation Day: Wednesday June 9 2004 Time: 8:30 to 10:00 | RM : 6D Chair: Wolfgang Roesner - IBM Corp., Austin, TX Organizers: Avi Ziv, Yaron Kashi This session discusses techniques for achieving high performance simulations for SoCs and other complex designs. The approaches vary from circuit aware architectural level simulation to efficient co-simulaton with hardware acceleration. 19.1 Communication-Efficient Hardware Acceleration for Fast Functional Simulation Speaker: Young-Il Kim, - KAIST Authors:Young-Il Kim, Wooseung Yang, Young-Su Kwon, , Chong-Min Kyung, - KAIST, Daejeon, Republic of Korea 19.2 A Fast Hardware/Software Co-Verification Method for System-on-a-Chip by Using a C/C++ Simulator and FPGA Emulator with Shared Register Communication Speaker: Yuichi Nakamura, - NEC Corp. Authors:Yuichi Nakamura, Kouhei Hosokawa, Ichiro Kuroda, , Ko Yoshikawa, - NEC Corp., Fuchu-City, Japan, , Takeshi Yoshimura, - Waseda Univ., Kitakyusyu-City, Japan 19.3 Circuit­Aware Architectural Simulation Speaker: Seokwoo Lee, - Univ. of Michigan Authors:Seokwoo Lee, Shidhartha Das, Valeria Bertacco, Todd Austin, David Blaauw, Trevor Mudge, - Univ. of Michigan, Ann Arbor, MI ********************************************************************************** Session: 20 | Title: Design for Manufacturability Day: Wednesday June 9 2004 Time: 8:30 to 10:00 | RM : 4 Chair: Ruiqi Tian - Motorola, Inc., Austin, TX Organizers: Charlie Chung-Ping Chen This session addresses design for manufacturability issues. The first paper presents a methodology to derive manufacturability-driven design rules so that RET effects can be anticipated during the design phase. The second paper presents an AltPSM-driven routing strategy that produces layouts which are phase correct. The third paper presents a timing methodology that takes systematic variations into account. Finally, the last paper presents a technique to reduce leakage and its variability. 20.1 Toward a Methodology for Manufacturability Driven Design Rule Exploration Speaker: Jie Yang, - Univ. of Michigan Authors:Luigi Capodieci - Advanced Micro Devices, Inc., Sunnyvale, CA, Puneet Gupta, , Andrew B. Kahng- Univ. of California at San Diego, La Jolla, CADennis Sylvester, , Jie Yang, - Univ. of Michigan, Ann Arbor, MI 20.2s Phase Correct Routing for Alternating Phase Shift Masks Speaker: Kevin Mccullen, - IBM Corp. Authors:Kevin Mccullen - IBM Corp., Essex Junction, VT 20.3 Toward a Systematic-Variation Aware Timing Methodology Speaker: Fook-Luen Heng, - IBM Corp. Authors:Puneet Gupta - Univ. of California at San Diego, La Jolla, CA, , Fook-Luen Heng- IBM Corp., Yorktown Heights, NY 20.4s Selective Gate-Length Biasing for Cost-Effective Runtime Leakage Control Speaker: Puneet Gupta, - Univ. of California at San Diego Authors:Puneet Gupta, Andrew B. Kahng, , Puneet Sharma- Univ. of California at San Diego, La Jolla, CA, Dennis Sylvester, - Univ. of Michigan, Ann Arbor, MI ********************************************************************************** Session: 21 | Title: Statistical Timing Analysis Day: Wednesday June 9 2004 Time: 10:30 to 12:00 | RM : 6A Chair: Anirudh Devgan - IBM Corp., Austin, TX Organizers: Charlie Chung-Ping Chen, Sani R. Nassif This session presents several new approaches to statistical static timing analysis. The first paper describes an incremental statistical timing approach based on a block-based traversal of the timing graph. The second paper proposes a way to compute the bounds on the distribution of circuit delay for timing graphs with arbitrary delay correlations. The third paper proposes an alternative approach to block-based statistical timing computation. 21.1 First-Order Incremental Block-Based Statistical Timing Analysis Speaker: Chandu Visweswariah, - IBM Corp. Authors:Chandu Visweswariah - IBM Corp., Yorktown Heights, NY, , Kaushik Ravindran- Univ. of California, Berkeley, CA, Kerim Kalafala, Steven G. Walker, , Sambasivan Narayan, - IBM Corp., Essex Junction, VT 21.2 Fast Statistical Timing Analysis with Arbitrary Delay Correlations Speaker: Michael Orshansky, - Univ. of Texas Authors:Michael Orshansky, , Arnab Bandyopadhyay- Univ. of Texas, Austin, TX 21.3 STAC: Statistical Timing Analysis with Correlation Speaker: Jiayong Le, - Carnegie Mellon Univ. Authors:Jiayong Le, Xin Li, , Lawrence T. Pileggi- Carnegie Mellon Univ., Pittsburgh, PA ********************************************************************************** Session: 22 | Title: Panel: System-Level Design: Six Success Stories in Search of an Industry Day: Wednesday June 9 2004 Time: 10:30 to 12:00 | RM : 6B Chair: Grant E. Martin - Tensilica, Inc., Santa Clara, CA Organizers: Francine Bacchini, Rita Glover System-level design is being touted as the holy grail that the electronics industry has long sought, but most offers have been disappointing because they seldom deliver results. Many designers are fed up with the "Blah, Blah" on system-level design as they are waiting for design facts. Why? It seems that major breakthroughs are happening thanks to the adoption of a standard direction for modeling design at higher than RTL level. These models are called TLM and new languages are being adopted (SystemC, SystemVerilog). The emergence of new standards may reshape completely the way design industry is organized. This panel will bring six speakers relating their success stories about design, starting at the system-level. The format is an educational Panel aimed at informing DAC attendees of the challenges (difficulties and pitfalls) and opportunities (sizable benefits and lessons learned from these experiences). 22.1 System Level Design: Six Success Stories in Search of an Industry Speaker: Pierre Paulin, - STMicroelectronicsArie Bernstein, - Intel Corp.Reinaldo A. Bergamaschi, - IBM Corp.Ramesh Chandra, - QUALCOMM, IncRaj Pawate, - Texas Instruments Authors: ********************************************************************************** Session: 23 | Title: New Ideas in Placement Day: Wednesday June 9 2004 Time: 10:30 to 12:00 | RM : 6C Chair: Patrick H. Madden - University of Kitakyushu, Kitakyushu, NY Organizers: Carl Sechen, Igor L. Markov This session covers a broad range of topics, including a novel geometric placement algorithm, a high-impact improvement of recursive bisection, and layout of quantum cellular automata (QCA). 23.1 Large-Scale Placement by Grid-Warping Speaker: Zhong Xiu, - Carnegie Mellon Univ.James D. Ma, - Carnegie Mellon Univ. Authors:Zhong Xiu, , James D. Ma- Carnegie Mellon Univ., Pittsburgh, PA, , Suzanne M. Fowler- Intel Corp., Chandler, AZ, Rob A. Rutenbar, - Carnegie Mellon Univ., Pittsburgh, PA 23.2 Placement Feedback: A Concept and Method for Better Min-Cut Placements Speaker: Sherief Reda, - Univ. of California at San Diego Authors:Andrew B. Kahng, , Sherief Reda- Univ. of California at San Diego, La Jolla, CA 23.3 Quantum-Dot Cellular Automata Partitioning: Problem Modeling and Solutions Speaker: Richard C. Murphy, - Univ. of Notre Dame Authors:Dominic A. Antonelli, Danny Z. Chen, Timothy J. Dysart, , Xiaobo S. Hu, - Univ. of Notre Dame, Notre Dame, IN, , Andrew B. Kahng, - Univ. of California at San Diego, La Jolla, CA, Peter M. Kogge, Richard C. Murphy, , Michael T. Niemier, - Univ. of Notre Dame, Notre Dame, IN ********************************************************************************** Session: 24 | Title: Model Order Reduction and Variational Techniques for Parasitic Analysis Day: Wednesday June 9 2004 Time: 10:30 to 12:00 | RM : 6D Chair: Luca Daniel - Massachusetts Institute of Tech, Cambridge, MA Organizers: Byron L. Krauter, Vikram Jandhyala This session presents new advances in model order reduction and variational techniques for parasitic analysis. The first paper presents an efficient project-and-balance scheme for passivity preserving model order reduction. The next paper presents a linear fractional transform based model for interconnect parametric uncertainty. The third paper extends closed-form moment-based delay and slew metrics to consider back-end process variation. The final paper presents a model order reduction scheme that exploits input information in massively coupled parasitic networks to produce compact models. 24.1 Passivity-Preserving Model Reduction via a Computationally Efficient Project-and-Balance Scheme Speaker: Ngai Wong, - Univ. of Hong Kong Authors:Ngai Wong - Univ. of Hong Kong, Hong Kong, Hong Kong, Venkataramanan Balakrishnan, , Cheng-Kok Koh- Purdue Univ., West Lafayette, IN 24.2 A Linear Fractional Transform (LFT) Based Model for Interconnect Parametric Uncertainty Speaker: Janet Wang, - Univ. of Arizona Authors:Janet Wang, , Omar A. Hafiz- Univ. of Arizona, Tucson, AZ, , Jun Li- eTop Design Technology, Inc., Sunnyvale, CA 24.3s Variational Delay Metrics for Interconnect Timing Analysis Speaker: Kanak Agarwal, - Univ. of Michigan Authors:Kanak Agarwal, Dennis Sylvester, , David Blaauw- Univ. of Michigan, Ann Arbor, MIFrank Liu, , Sani Nassif, - IBM Corp., Austin, TX, , Sarma Vrudhula, - Univ. of Arizona, Tucson, AZ 24.4s Exploiting Input Information in a Model Reduction Algorithm for Massively Coupled Parasitic Networks Speaker: Joel R. Phillips, - Cadence Berkeley Labs. Authors:Miguel Silveira - INESC, Lisbon, Portugal, , Joel R. Phillips- Cadence Berkeley Labs., San Jose, CA ********************************************************************************** Session: 25 | Title: Compilation Techniques for Embedded Applications Day: Wednesday June 9 2004 Time: 10:30 to 12:00 | RM : 4 Chair: Heinrich Meyr - RWTH Aachen/CoWare, Inc., Aachen, DEU Organizers: Mahmut Kandemir The increasing software content in embedded systems makes it imperative to consider code optimizations. These techniques are of key importance to the design of heterogeneous application specific SoCs. The papers in this session range from compilation for custimized memory architectures to instruction set design. 25.1 Automatic Translation of Software Binaries onto FPGAs Speaker: Gaurav Mittal, - Northwestern Univ. Authors:Gaurav Mittal, David C. Zaretsky, Xiaoyong Tang, , Prithviraj Banerjee, - Northwestern Univ., Evanston, IL 25.2 Area-Efficient Instruction Set Synthesis for Reconfigurable System-on-Chip Designs Speaker: Philip Brisk, - Univ. of California Authors:Philip Brisk, Adam Kaplan, , Majid Sarrafzadeh- Univ. of California, Los Angeles, CA 25.3 Data Compression for Improving SPM Behavior Speaker: Mahmut Kandemir, - Penn State Univ. Authors:Ozcan Ozturk, , Mahmut Kandemir- Penn State Univ., University Park, PA, , Ilteris Demirkiran- Syracuse Univ., Syracuse, NYGuangyu Chen, , Mary Jane Irwin, - Penn State Univ., University Park, PA ********************************************************************************** Session: 26 | Title: Special Session: Platform-Based System Design Day: Wednesday June 9 2004 Time: 2:00 to 4:00 | RM : 6A Chair: Sujit Dey - Univ. of California at San Diego, La Jolla, CA Organizers: Sujit Dey Rising design complexity and NRE/manufacturing costs of ASICs pushes towards reuse. Platforms are emerging as an alternative to System-on-Chips rather than reuse of components, use of platforms potentially eliminates need for backend design. This special session will analyze and evaluate the characteristics and strengths/weaknesses of different types of platforms and their applicability to different segments of the semiconductor industry. Key issues regarding their adoption, including EDA and Software Support will also be addressed. 26.1s Platform Based Design: Does it Answer the Entire SoC Challenge? Speaker: Gary Smith, - Gartner Dataquest Authors:Gary Smith - Gartner Dataquest, San Jose, CA 26.2 Nomadic Platform Approach for Wireless Mobile Multimedia Speaker: Mark Hopkins, - STMicroelectronics Authors:Mark Hopkins - STMicroelectronics, San Diego, CA 26.3 Benefits and Challenges of Platform Based Design Speaker: Alberto L. Sangiovanni-Vincentelli, - Univ. of California Authors:Alberto L. Sangiovanni-Vincentelli, , Luca Carloni- Univ. of California, Berkeley, CA, , Fernando De Bernadinis- Dipartimento di Ingegneria dell'Informazione - University of Pisa, Pisa, Italy, Marco Sgroi, - DoCoMo Euro Labs, Munich, Germany 26.4 Trends in the Use of Re-Configurable Platforms Speaker: Max Baron, - In-Stat/MDR Authors:Max Baron - In-Stat/MDR, San Jose , CA 26.5s Discussion: Q&A Speaker: Authors: ********************************************************************************** Session: 27 | Title: Innovations in Logic Synthesis Day: Wednesday June 9 2004 Time: 2:00 to 4:00 | RM : 6B Chair: Rajeev Murgai - Fujitsu Labs., Sunnyvale, CA Organizers: Marek Perkowski, Soha Hassoun Logic synthesis continues to play a critical role in Design Automation. The first paper presents a novel recursive approach to finding a minimal function that repersents a Boolean relationship. The second paper describes a fast technique for computing approximate CODCs for large circuits based on computing the CODCs of smaller sub-networks. The third paper discusses BDD-based functional decomposition into a cascasde of LUTs with intermediate outputs. The fourth paper proposes a novel algorithm to compute symmetries in incompletely specified functions. The final paper introduces new circuit restructuring techniques based on implicit enumeration of all possible restructuring patterns. 27.1 A Recursive Paradigm to Solve Boolean Relations Speaker: David Bañeres, - Univ. Politecnica Catalunya Authors:David Bañeres, , Jordi Cortadella- Univ. Politecnica Catalunya, Barcelona, Spain, , Mike Kishinevsky- Intel Corp., Hillsboro, OR 27.2 A Robust Algorithm for Approximate Compatible Observability Don't Care (CODC) Computation Speaker: Sunil Khatri, - Univ. of Colorado Authors:Nikhil Saluja, , Sunil Khatri- Univ. of Colorado, Boulder, CO 27.3 A Method to Decompose Multiple-Output Logic Functions Speaker: Tsutomu Sasao, - Kyushu Institute of Tech. Authors:Tsutomu Sasao, , Munehiro Matsuura- Kyushu Institute of Tech., Iizuka, Japan 27.4s Symmetry Detection for Incompletely Specified Functions Speaker: Jia-Hung Chen, - Fu Jen Catholic Univ. Authors:Kuo-Hua Wang, , Jia-Huang Chen- Fu Jen Catholic Univ., Taipei, Taiwan 27.5s Implicit Enumeration of Structural Changes in Circuit Optimization Speaker: Victor N. Kravets, - IBM Corp. Authors:Victor N. Kravets, , Prabhakar Kudva- IBM Corp., Yorktown Heights, NY ********************************************************************************** Session: 28 | Title: Yield Estimation and Optimization Day: Wednesday June 9 2004 Time: 2:00 to 4:00 | RM : 6C Chair: Vivek De - Intel Corporation, Hillsboro, OR Organizers: Michael Orshansky, Sudhakar Bobba Process variability has been at the forefront of the design and EDA communities. The recent work on statistical static timing is an example of the response of the EDA community to this important area. This session is an indicator of the next wave of research in this area, one which will begin to apply these algorithms to estimate and optimize the timing yield of a design. 28.1 Parametric Yield Estimation Considering Leakage Variability Speaker: Rajeev R. Rao, - Univ. of Michigan Authors:Rajeev R. Rao - Univ. of Michigan, Ann Arbor, MI, , Anirudh Devgan- IBM Corp., Austin, TX, David Blaauw, , Dennis Sylvester, - Univ. of Michigan, Ann Arbor, MI 28.2 A Methodology to Improve Timing Yield in the Presence of Process Variations Speaker: Sreeja Raj, - Univ. of Arizona Authors:Sreeja Raj, Sarma Vrudhula, , Janet M. Wang- Univ. of Arizona, Tucson, AZ 28.3 Novel Sizing Algorithm for Yield Improvement under Process Variation in Nanometer Technology Speaker: Seung Hoon Choi, - Intel Corp. Authors:Seung Hoon Choi - Intel Corp., Hillsboro, OR, Bipul C. Paul, , Kaushik Roy- Purdue Univ., West Lafayette, IN 28.4 Statistical Timing Analysis Based on a Timing Yield Model Speaker: Farid N. Najm, - Univ. of Toronto Authors:Farid N. Najm - Univ. of Toronto, Toronto, ON, Canada, , Noel Menezes- Intel Corp., Hillsboro, OR ********************************************************************************** Session: 29 | Title: High-Level Techniques for Signal Processing Day: Wednesday June 9 2004 Time: 2:00 to 4:00 | RM : 6D Chair: Stephen A. Edwards - Columbia Univ., New York, NY Organizers: Reinaldo A. Bergamaschi, Stephen A. Edwards The papers in this session deal with high-level synthesis problems that appear in signal processing applications. The first paper applies transaction-level modeling to DSP applications. The next three papers deal with choosing word lengths in hardware implementations of DSP applications. The last paper synthesizes error-correcting codes that greatly reduce wiring costs. 29.1 System Design for DSP Applications in Transaction Level Modeling Paradigm Speaker: Abhijit K. Deb, - Royal Institute of Tech. Authors:Abhijit K. Deb, Axel Jantsch, , Johnny Oberg- Royal Institute of Tech., Kista, Sweden 29.2 An Analytical Approach for Dynamic Range Estimation Speaker: Bin Wu, - Univ. of Toronto Authors:Bin Wu, Jianwen Zhu, , Farid N. Najm- Univ. of Toronto, Toronto, ON, Canada 29.3 Automated Fixed-Point Data-Type Optimization Tool for Signal Processing and Communication Systems Speaker: Changchun Shi, - Univ. of California Authors:Changchun Shi, , Robert W. Brodersen- Univ. of California, Berkeley, CA 29.4s An Algorithm for Converting Floating-Point Computations to Fixed-Point in MATLAB Based FPGA Design Speaker: Sanghamitra Roy, - Northwestern Univ. Authors:Sanghamitra Roy, , Prith Banerjee- Northwestern Univ., Evanston, IL 29.5s Synthesizing Interconnect-Efficient Low Density Parity Check Codes Speaker: Marghoob Mohiyuddin, - Univ. of Texas Authors:Marghoob Mohiyuddin, Amit Prakash, , Adnan Aziz- Univ. of Texas, Austin, TX, Wayne Wolf, - Princeton Univ., Princeton, NJ ********************************************************************************** Session: 30 | Title: Advanced Test Solutions Day: Wednesday June 9 2004 Time: 2:00 to 4:00 | RM : 4 Chair: Paolo Prinetto - Politecnico di Torino, Torino, Italy Organizers: TM Mak, Yervant Zorian Novel and efficient solutions to test for very deep submicron chips are presented in this session. These solutions address a number of optimization factors, including: reducing power, identifying critical paths, diagnosing FPGA's faults and optimizing silicon debug. 30.1 On Path-Based Learning and its Applications in Delay Test and Diagnosis Speaker: Li-C. Wang, - Univ. of California Authors:Li-C. Wang - Univ. of California, Santa Barbara, CA, , TM Mak- Intel Corp., Santa Clara, CA, , Kwang-Ting Cheng- Univ. of California, Santa Barbara, CA, Magdy S. Abadir, - Motorola, Inc., Austin, TX 30.2 Efficient On-Line Testing of FPGAs with Provable Diagnosabilities Speaker: Shantanu Dutt, - Univ. of Illinois Authors:Vinay Verma - Xilinx, Inc., San Jose, CA, Shantanu Dutt, , Vishal Suthar- Univ. of Illinois, Chicago, IL 30.3 On Test Generation for Transition Faults with Minimized Peak Power Dissipation Speaker: Wei Li, - Univ. of Iowa Authors:Wei Li, , Sudhakar M. Reddy- Univ. of Iowa, Iowa City, IA, , Irith Pomeranz- Purdue Univ., West Lafayette, IN 30.4s A New State Assignment Technique for Testing and Low Power Speaker: Sungju Park, - Hanyang Univ. Authors:Sungju Park, , Sangwook Cho- Hanyang Univ., Ansan, Republic of Korea, , Seiyang Yang- Pusan Univ., Pusan, Republic of Korea, Maciej Ciesielski, - Univ. of Massachusetts, Amherst, MA 30.5s Automatic Generation of Breakpoint Hardware for Silicon Debug Speaker: Bart Vermeulen, - Philips Research Labs. Authors:Bart Vermeulen - Philips Research Labs., Eindhoven, Netherlands, , Mohammad Z. Urfianto- Royal Institute of Tech., Kista, Sweden, , Sandeep K. Goel- Philips Research Labs., Eindhoven, Netherlands ********************************************************************************** Session: 31 | Title: Advances in Boolean Analysis Techniques Day: Wednesday June 9 2004 Time: 4:30 to 6:30 | RM : 6A Chair: Aarti Gupta - NEC Corp., Princeton, NJ Organizers: Pei-Hsin Ho, Tony Ma Recent years have witnessed significant advances in the scalability and applicability of Boolean reasoning methods in a variety of EDA problems. Papers in this session represent significant extensions to the state-of-the-art technology in this area. The first paper proposes a SAT-based method for diagnosing infeasibility. The second paper uses re-parametrization to improve symbolic simulation. The third paper presents efficient symmetry detection methods. The last two papers describe methods for enhancing bounded model checking and combinational equivalence checking. 31.1 AMUSE: A Minimally-Unsatisfiable Subformula Extractor Speaker: Maher N. Mneimneh, - Univ. of Michigan Authors:Yoonna Oh, Maher N. Mneimneh, Zaher S. Andraus, Karem A. Sakallah, , Igor L. Markov, - Univ. of Michigan, Ann Arbor, MI 31.2 A SAT-Based Algorithm for Reparameterization in Symbolic Simulation Speaker: Pankaj P. Chauhan, - Carnegie Mellon Univ. Authors:Pankaj P. Chauhan, Edmund M. Clarke, , Daniel Kroening- Carnegie Mellon Univ., Pittsburgh, PA 31.3 Exploiting Structure in Symmetry Detection for CNF Speaker: Paul T. Darga, - Univ. of Michigan Authors:Paul T. Darga, Mark H. Liffiton, Karem A. Sakallah, , Igor L. Markov, - Univ. of Michigan, Ann Arbor, MI 31.4s Refining the SAT Decision Ordering for Bounded Model Checking Speaker: Chao Wang, - Univ. of Colorado Authors:Chao Wang, HoonSang Jin, Gary D. Hachtel, , Fabio Somenzi, - Univ. of Colorado, Boulder, CO 31.5s Efficient Equivalence Checking with Partitions and Hierarchical Cut-Points Speaker: Lisa R. McIlwain, - Synopsys, Inc. Authors:Demosthenes Anastasakis, , Lisa R. Mcilwain- Synopsys, Inc., Hillsboro, OR, , Slawomir Pilarski- Univ. of Washington, Tacoma, WA ********************************************************************************** Session: 32 | Title: Panel: Were the Good Old Days all that Good? EDA Then and Now Day: Wednesday June 9 2004 Time: 4:30 to 6:30 | RM : 6B Chair: William H. Joyner, Jr. - IBM Corp./SRC, Research Triangle Park, NC Organizers: Shishpal Rawat, William H. Joyner, Jr. A long, long time ago, in a laboratory far, far away, EDA researchers and developers used paper tape instead of Linux, rubylith instead of GDS II, yellow wires instead of ten levels of metal. Sitting around a potbellied stove, in their rocking chairs, practitioners of that era (and this) will offer insight into why some great ideas were immediately put into practice while others stayed on the drawing board or in the ivory tower. They will share remembrances of things past, of simpler days when foundries made steel, when options meant CMOS or bipolar, when real parts were measured instead of benchmarks touted. Their stories of what it was like, what has changed, and whether the "good old days" were then or now will be followed by questions and, possibly, answers. 32.1 Were the Good Old Days all That Good? EDA Then and Now Speaker: John Darringer, - IBM Corp.Hugo De Man, - IMECDaniel Gajski, - Univ. of CaliforniaCarl Harris, - Kluwer Academic PublishersP.O. Pistilli, - MP Associates, Inc. Authors: ********************************************************************************** Session: 33 | Title: Power Optimization for Real-Time and Media-Rich Embedded Systems Day: Wednesday June 9 2004 Time: 4:30 to 6:30 | RM : 6C Chair: Sujit Dey - Univ. of California at San Diego, La Jolla, CA Organizers: Sujit Dey Real-time, multimedia applications promise to be strong drivers for mobile, battery-constrained embedded systems. However, these applications are highly computation intensive, and thereby energy demanding. This session offers energy modeling and optimization techniques for several real-time and multimedia systems, including MPEG decoding, video-array based tracking systems, watermarking for image transmission, and fault-tolerant real-time systems. 33.1 Off-Chip Latency-Driven Dynamic Voltage and Frequency Scaling for an MPEG Decoding Speaker: Kihwan Choi, - Univ. of Southern California Authors:Kihwan Choi, Ramakrishna Soma, , Massoud Pedram- Univ. of Southern California, Los Angeles, CA 33.2 Energy-Aware Deterministic Fault Tolerance in Distributed Real-Time Systems Speaker: Ying Zhang, - Duke Univ. Authors:Ying Zhang - Duke Univ., Durham, NC, , Robert Dick- Northwestern Univ., Evanston, IL, , Krishnendu Chakrabarty- Duke Univ., Durham, NC 33.3 Proxy-Based Task Partitioning of Watermarking Algorithms for Reducing Energy Consumption in Mobile Devices Speaker: Arun Kejariwal, - Univ. of California Authors:Arun Kejariwal, Sumit Gupta, Alexandru Nicolau, , Nikil Dutt, - Univ. of California, Irvine, CA, , Rajesh Gupta, - Univ. of California at San Diego, La Jolla, CA 33.4s Adaptive Data Partitioning for Ambeint Multimedia Speaker: Xiaoping Hu, - Carnegie Mellon Univ. Authors:Xiaoping Hu, , Radu Marculescu- Carnegie Mellon Univ., Pittsburgh, PA 33.5s Energy Characterization of Filesystems for Diskless Embedded Systems Speaker: Siddharth Choudhuri, - Univ. of California Authors:Siddharth Choudhuri - Univ. of California, Irvine, CA, , Rabi Mahapatra- Texas A&M Univ., College Station, TX ********************************************************************************** Session: 34 | Title: Latency Tolerance and Asynchronous Design Day: Wednesday June 9 2004 Time: 4:30 to 6:30 | RM : 6D Chair: Marios Papaefthymiou - Univ. of Michigan, Ann Arbor, MI Organizers: James C. Hoe, Leon Stok This session presents five papers in the areas of latency tolerance and asynchronous design. The first paper describes a technique to automatically correct the functionality of wire-pipelined circuits. The second paper describes an approach to minimizing the latency management overhead in statically schedulable designs. The third paper proposes approaches to estimate wire length and congestions during logic synthesis. The fourth paper presents optimizations to asynchronous logic synthesis by "de-synchronization". The final paper presents a fast algorithm for hazard detection in combinational circuits. 34.1 A Method for Correcting the Functionality of a Wire-Pipelined Circuit Speaker: Vidyasagar Nookala, - Univ. of Minnesota Authors:Vidyasagar Nookala, , Sachin S. Sapatnekar- Univ. of Minnesota, Minneapolis, MN 34.2 A New Approach to Latency Insensitive Design Speaker: Luca Macchiarulo, - Politecnico di Torino Authors:Luca Macchiarulo, , Mario R. Casu- Politecnico di Torino, Torino, Italy 34.3 Pre-Layout Wire Length and Congestion Estimation Speaker: Qinghua Liu, - Univ. of California Authors:Qinghua Liu, , Malgorzata Marek-Sadowska- Univ. of California, Santa Barbara, CA 34.4s The Best of Both Worlds: The Efficient Asynchronous Implementation of Synchronous Specifications Speaker: Abhijit Davare, - Univ. of California Authors:Abhijit Davare - Univ. of California, Berkeley, CA, , Kelvin Lwin- Cadence Design Systems, Inc., San Jose, CA, , Alex Kondratyev- Cadence Berkeley Labs., Berkeley, CA, Alberto L. Sangiovanni-Vincentelli, - Univ. of California, Berkeley, CA 34.5s Fast Hazard Detection in Combinational Circuits Speaker: Cheoljoo Jeong, - Columbia Univ. Authors:Cheoljoo Jeong, , Steven M. Nowick- Columbia Univ., New York, NY ********************************************************************************** Session: 35 | Title: New Technologies in System Design Day: Wednesday June 9 2004 Time: 4:30 to 6:30 | RM : 4 Chair: Petru Eles - Linkoping Univ., Linkoping, SWE Organizers: Ahmed A. Jerraya, Gila Kamhi This session covers a broad set of ideas in system design, ranging from nanotechnologies to bus usage analysis. The first paper presents strategies for successful design given the anticipated high-defect rate of future nanotechnologies. The next three papers tackle the challenges of architectural synthesis from both the design and verification view points. The last paper provides throughput and power dissipation analysis of AMBA AHB bus usage. 35.1 Defect Tolerant Probabilistic Design Paradigm for Nanotechnologies Speaker: Margarida Jacome, - Univ. of Texas Authors:Margarida Jacome, Chen He, Gustavo deVeciana, , Steve Bijansky, - Univ. of Texas, Austin, TX 35.2 Architecture-Level Synthesis for Automatic Interconnect Pipelining Speaker: Yiping Fan, - Univ. of California Authors:Jason Cong, Yiping Fan, , Zhiru Zhang- Univ. of California, Los Angeles, CA 35.3 Automatic Generation of Equivalent Architecture Model from Functional Specification Speaker: Samar Abdi, - Univ. of California Authors:Samar Abdi, , Daniel Gajski- Univ. of California, Irvine, CA 35.4s Divide-and-Concatenate: An Architecture Level Optimization Technique for Universal Hash Functions Speaker: Bo Yang, - Polytechnic Univ. Authors:Bo Yang, , Ramesh Karri- Polytechnic Univ., Brooklyn, NY, , David A. Mcgrew- Cisco Systems, Inc., San Jose, CA 35.5s Performance Analysis of Different Arbitration Algorithms of the AMBA AHB BUS Speaker: Massimo Conti, - Univ. Politecnica della Marche Authors:Massimo Conti, Marco Caldari, Giovanni B. Vece, Simone Orcioni, , Claudio Turchetti, - Univ. Politecnica delle Marche, Ancona, Italy ********************************************************************************** Session: 36 | Title: Special Session: BioMEMS Day: Thursday June 10 2004 Time: 8:30 to 10:00 | RM : 6A Chair: Andrew B. Kahng - University Of California San Diego, La Jolla, CA Organizers: Jacob K. White The variety of applications for BioMEMS and the potential volumes involved has started to influence CAD development. Because almost all products are created by physical prototyping and have huge times-to-market, there is a substantial opportunity for address new CAD challenges: developing hierarchy, topology synthesis, shape optimization and layout, circuit simulation, and more. 36.1 Design Tools for BioMEMS Speaker: Tom Korsmeyer, - Coventor, Inc. Authors:Tom Korsmeyer, Jun Zeng, , Ken Greiner- Coventor, Inc., Cambridge, MA 36.2 Atomistic and Multiscale Techniques for Bio-Nano Devices Speaker: Narayan Aluru, - Univ. of Illinois , Urbana-Champaign Authors:Narayan Aluru - Univ. of Illinois, Urbana, IL 36.3 CAD Challenges in BioMEMS Design Speaker: Jacob White, - Massachusetts Institute of Tech. Authors:Jacob White - Massachusetts Institute of Tech., Cambridge, MA ********************************************************************************** Session: 37 | Title: Panel: Will Moore's Law Rule in the Land of Analog? Day: Thursday June 10 2004 Time: 8:30 to 10:00 | RM : 6B Chair: Rob A. Rutenbar - Carnegie Mellon Univ., Pittsburgh, PA Organizers: Rob A. Rutenbar Once upon a time there was a wise and benevolent ruler whose Law multiplied his subjects’ wealth and happiness--about 2X, every couple of years, but the kingdom was divided. Those in the happy hamlet of Digital got fatter (and faster), year after year. Not so the talented artisans in the town of Analog complained constantly about "voltage headroom", "variability", "noise", "matching", "kT/C limits", the rising costs of supporting their neighbors' insatiable addiction to shrinking transistors, and how the grass looked greener just over the border, in Silicon-Germania. So, what's a King to do? Will we see billion transistor chips with integrated RF made from transistors that are 25 atoms wide? Or will the peasants in the land of Analog really revolt? 37.1 Will Moore's Law Rule in the Land of Analog Speaker: Teresa Meng, - Stanford Univ./AtherosCharlie Sodini, - Massachusetts Institute of Tech.Jim Wieser, - National Semiconductor Corp.Robert Pitts, - Texas Instruments, Inc.Ernesto Perea, - STMicroelectronics Authors: ********************************************************************************** Session: 38 | Title: Floorplanning Day: Thursday June 10 2004 Time: 8:30 to 10:00 | RM : 6C Chair: Malgorzata Marek-Sadowska - Univ. of California, Santa Barbara, CA Organizers: Chung-Kuan Cheng, Frank M. Johannes The session advocates floorplanning for architecture-level and layout optimization. In the first paper, a microarchitectural floorplanner is presented that considers both the impact of wire delay and architectural behavior. The second paper increases instructions per cycle using a trajectory piece-wise linear model. A representation to tackle the floorplanning of triangular objects that achieves efficient area utilization is introduced in the third paper. 38.1 Profile-Guided Microarchitectural Floorplanning for Deep Submicron Processor Design Speaker: Mongkol Ekpanyapong, - Georgia Institute of Tech. Authors:Mongkol Ekpanyapong, , Jacob R. Minz- Georgia Institute of Tech., Atlanta, GA, , Thaisiri Watewai- Univ. of California, Berkeley, CAHsien-Hsin S. Lee, , Sung Kyu Lim, - Georgia Institute of Tech., Atlanta, GA 38.2 Floorplanning Optimization with Trajectory Piecewise-Linear Model for Pipelined Interconnects Speaker: Changbo Long, - Univ. of California Authors:Changbo Long, Lucanus J. Simonson, Weiping Liao, , Lei He, - Univ. of California, Los Angeles, CA 38.3 A Packing Algorithm for Non-Manhattan Hexagon/Triangle Placement by Using an Adaptive O-Tree Representation Speaker: Chunghui Li Authors:Jing Li, Bo Yang, , Tan Yan- Univ. of Electronic Sci. & Tech. of China, Chengdu, China, Juebang Yu, , China, , Chunhui Li, - Cadence Design Systems Inc., San Jose, CA ********************************************************************************** Session: 39 | Title: Issues in Timing Analysis Day: Thursday June 10 2004 Time: 8:30 to 10:00 | RM : 6D Chair: David Hathaway - IBM Corp., Essex Junction, VT Organizers: Kenneth L. Shepard, Sudhakar Bobba This session considers several issues in the static timing analysis of digital integrated circuits. In the first paper, the effect of power supply variations on timing is analyzed. The second paper offers a statistical gate delay model that considers the effects of multiple input switching. The final paper in this session proposes a new timing analysis algorithm using a two-pass traversal of the timing graph. 39.1 Worst-Case Circuit Delay Taking into Account Power Supply Variations Speaker: Dionysios Kouroussis, - Univ. of Toronto Authors:Dionysios Kouroussis, Rubil Ahmadi, , Farid N. Najm- Univ. of Toronto, Toronto, ON, Canada 39.2 Statistical Gate Delay Model Considering Multiple Input Switching Speaker: Aseem B. Agarwal, - Univ. of Michigan Authors:Aseem B. Agarwal - Univ. of Michigan, Ann Arbor, MI, , Florentin Dartu- Intel Corp., Hillsboro, OR, , David Blaauw- Univ. of Michigan, Ann Arbor, MI 39.3 Static Timing Analysis Using Backward Signal Propagation Speaker: Dongwoo Lee, - Univ. of Michigan Authors:Dongwoo Lee - Univ. of Michigan, Ann Arbor, MI, , Vladimir Zolotov- Motorola, Inc., Austin, TX, , David Blaauw- Univ. of Michigan, Ann Arbor, MI ********************************************************************************** Session: 40 | Title: Special Session: ISSCC Highlights Day: Thursday June 10 2004 Time: 8:30 to 10:00 | RM : 4 Chair: Grant E. Martin - Tensilica, Inc., Santa Clara, CA Organizers: Grant E. Martin 40.1 Design and Implementation of the POWER5 Microprocessor Speaker: Joshua Friedrich, - IBM Corp. Authors:Joachim Clabes, , Joshua Friedrich- IBM Corp., Austin, TX 40.2 A Dual Core 64b UltraSPARC Microprocessor for Dense Server Applications Speaker: Toshinari Takayanagi, - Sun Microsystems, Inc. Authors:Toshinari Takayanagi, Jinuk Luke Shin, Bruce Petrick, Jeffrey Su, , Ana Sonia Leon, - Sun Microsystems, Inc., Sunnyvale, CA 40.3 Low-Voltage-Swing Logic Circuits for a Pentium 4 Processor Integer Core Speaker: Micah Barany , - Intel Corp. Authors:Daniel Deleganes - Intel Corp., Hillsboro, OR ********************************************************************************** Session: 41 | Title: Special Session: Multiprocessor SoC MPSoC Solutions/Nightmare Day: Thursday June 10 2004 Time: 10:30 to 12:00 | RM : 6A Chair: Grant E. Martin - Tensilica, Inc., Santa Clara, CA Organizers: Grant E. Martin What ? (Topic) – Multi-processor System-on-Chip is the future of SoC and indeed of much of IC Design. A network of heterogeneous processors – RISCs, DSPs, ASIPs, and dedicated function blocks – interconnected by a Network-on-Chip (NoC) fabric seems destined to be a key architecture for MPSoC. However, we are a long, long way from knowing how to effectively design MPSoC and obtaining the right tools, methods and approaches. This Special session will first give an overview of MPSoC and key design problems and then have a couple of talks outlining some potential solutions. Why ? (Motivation, Importance, Interest) - SoCs are already “MP” if we take the now classical RISC+DSP combination used in many handsets and consumer products. We currently lack effective means and tools to design even this simple combination, so the issues of how to map complex applications to MPSoC with 4, 10 or many 10’s of processors is a daunting one. However, leading researchers and companies are beginning to identify solutions to key parts of this puzzle, and this special session will educate designers on what is possible and what will come. 41.1 The Future of Multiprocessor Systems-on-Chips Speaker: Wayne Wolf, - Princeton Univ. Authors:Wayne Wolf - Princeton Univ., Princeton, NJ 41.2 Heterogeneous MP-SoC--The Solution to Energy-Efficient Signal Processing Speaker: Heinrich Meyr, - Aachen Univ. of Tech Authors:Heinrich Meyr - Aachen Univ. of Tech., Aachen, Germany 41.3 Flexible Architectures for Engineering Successful MPSoCs Speaker: Steve Leibson, - Tensilica, Inc. Authors:Steve Leibson - Tensilica, Inc., Santa Clara, CA ********************************************************************************** Session: 42 | Title: Panel: Is Statistical Timing Statistically Significant? Day: Thursday June 10 2004 Time: 10:30 to 12:00 | RM : 6B Chair: Andrew B. Kahng - Univ. of California at San Diego, La Jolla, CA Organizers: Rich Goldman, Kurt Keutzer Process variations that affect critical electrical parameters leading to changes in circuit performance have always posed significant challenges to semiconductor design. In the past, in-die process variation was relatively small, and methods such as corner-based analysis were sufficient. This allowed timing analysis tools to calculate delays and slews in a straightforward way. As statistical variation increases, will corner-casing lead to too much conservatism, or are the advantages of statistical timing analysis overstated? 42.1 Is Statistical Timing Statistically Significant? Speaker: Chandu Visweswariah, - IBM Corp.Ahsan Bootehsaz, - Synopsys, Inc.Ed Chen, - TSMCClive Bittlestone, - Texas Instruments, Inc.Lou Scheffer, - Cadence Design Systems, Inc. Authors: ********************************************************************************** Session: 43 | Title: Timing Issues in Placement Day: Thursday June 10 2004 Time: 10:30 to 12:00 | RM : 6C Chair: Bill Halpin - Synplicity, Inc., Sunnyvale, CA Organizers: Carl Sechen, Phiroze Parakh This session presents algorithmic improvements in performance-driven physical synthesis. This includes buffering and logic replication, as well as a new timing-driven placement algorithm. 43.1 Modeling Repeaters Explicitly within Analytical Placement Speaker: Prashant Saxena, - Intel Corp. Authors:Prashant Saxena - Intel Corp., Hillsboro, OR, , Bill Halpin- Synplicity, Inc., Sunnyvale, CA 43.2 Quadratic Placement Using an Improved Timing Model Speaker: Bernd Obermeier, - Technical Univ. of Munich Authors:Bernd Obermeier, , Frank M. Johannes- Technical Univ. of Munich, Munich, Germany 43.3 An Approach to Placement-Coupled Logic Replication Speaker: Milos Hrkic, - Univ. of Illinois Authors:Milos Hrkic, John Lillis, , Giancarlo Beraudo- Univ. of Illinois, Chicago, IL ********************************************************************************** Session: 44 | Title: Design Methodologies for ASIPs Day: Thursday June 10 2004 Time: 10:30 to 12:00 | RM : 6D Chair: Masaharu Imai - Osaka Univ., Toyonaka, Japan Organizers: Joachim Gerlach, Margarida Jacome Application Specific Instruction Set Processors (ASIPs) offer a good trade-off between flexibility, performance and energy efficiency. However, their effectiveness relies on the ability to properly customize processors to target classes of embedded applications and create the corresponding development environments, in reasonable time. The first paper enhances a well known architecture description language so that compilers and instruction set simulators can all be generated from a single, consistent model. The second and third papers explore several aspects of extending a processor's instruction set, including mechanisms for instruction set selection and inclusion of local memory elements. 44.1 A Novel Approach for Flexible and Consistent ADL-Driven ASIP Design Speaker: Gunnar Braun, - CoWare, Inc. Authors:Gunnar Braun - CoWare, Inc., Aachen, Germany, , Weihua Sheng- Institute for Integrated Systems, Aachen, Germany, , Achim Nohl- CoWare, Inc., Aachen, GermanyJianjiang Ceng, Manuel HohenauerHanno Scharwaechter, Rainer Leupers, , Heinrich Meyr, - Institute for Integrated Systems, Aachen, Germany 44.2 Characterizing Embedded Applications for Instruction-Set Extensible Processors Speaker: Pan Yu, - National Univ. of Singapore Authors:Pan Yu, , Tulika Mitra- National Univ. of Singapore, Singapore, Singapore 44.3 Introduction of Local Memory Elements in Instruction Set Extensions Speaker: Partha Biswas, - Univ. of California Authors:Partha Biswas - Univ. of California, Irvine, CA, Vinay Choudhary, Kubilay Atasu, Laura Pozzi, , Paolo Ienne, - Swiss Federal Institute of Technology, Lausanne, Switzerland, , Nikil Dutt, - Univ. of California, Irvine, CA ********************************************************************************** Session: 45 | Title: FPGA-Based Systems Day: Thursday June 10 2004 Time: 10:30 to 12:00 | RM : 4 Chair: Katherine Compton - Univ. of Wisconsin, Madison, WI Organizers: Jens Palsberg, Scott Hauck The heterogeneity of newer FPGAs is driving new classes of systems, and corresponding problems, for the FPGA CAD designer. With multiple resources, traditional algorithms such as partitioning must be reformulated to deal with these constraints. Power and power minimization is also crucial, forcing changes in architecture and algorithms. These new architectures give rise to new uses, such as mixed-mode simulators. 45.1 FPGA Power Reduction Using Configurable Dual-Vdd Speaker: Fei Li, - Univ. of California Authors:Fei Li, Yan Lin, , Lei He- Univ. of California, Los Angeles, CA 45.2 Multi-Resource Aware Partitioning Algorithms for FPGAs with Heterogeneous Resources Speaker: Navaratnasothie Selvakkumaran, - Univ. of Minnesota Authors:Navaratnasothie Selvakkumaran - Univ. of Minnesota, Minneapolis, MN, Abishek Ranjan, , Salil Raje- Hier Design Inc., Santa Clara, CA, George Karypis, - Univ. of Minnesota, Minneapolis, MN 45.3 An SoC Design Methodology Using FPGA and Embedded Microprocessors Speaker: Nobuyuki Ohba, - IBM Corp. Authors:Nobuyuki Ohba, , Kohji Takano- IBM Corp., Yamato, Japan ********************************************************************************** Session: 46 | Title: Special Session: Security as a New Dimension in Embedded System Design Day: Thursday June 10 2004 Time: 2:00 to 4:00 | RM : 6A Chair: Srivaths Ravi - NEC Corp., Princeton, NJ Organizers: Srivaths Ravi The growing number of instances of breaches in information security in the last few years has created a compelling case for efforts towards secure electronic systems. Embedded systems, which will be ubiquitously used to capture, store, manipulate, and access data of a sensitive nature, pose several unique and interesting security challenges. This special session is intended to introduce the challenges involved in designing secure embedded systems to embedded system designers and design tool developers. The session will provide a unified and holistic view of embedded system security: "Security is often mis-construed by designers as the hardware or software implementation of specific cryptographic algorithms and security protocols, whereas in reality it is an entirely new metric that designers should consider throughout the design process, along with other metrics such as cost, performance, power, etc." Speakers will provide a clear introduction of typical functional security requirements for embedded systems from an end-user perspective. They will identify the implied challenges for embedded system architects, as well as hardware and software designers (e.g., tamper-resistant embedded system design, processing requirements for security, impact of security on battery life for battery-powered systems, etc). The speakers will also provide an overview of solution techniques to address these challenges, drawing from both current practice and emerging research, and identify open research problems that will require innovations in embedded system architecture and design methodologies. 46.1 Security Challenges in Embedded System Design Speaker: Anand Raghunathan, - NEC Corp. Authors:Anand Raghunathan - NEC Corp., Princeton, NJ 46.2 Exploiting Embedded Software Speaker: Gary McGraw, - Cigital, Inc. Authors:Gary McGraw - Cigital, Inc., Dulles, VA 46.3 Processor Architectures for Efficient Secure Information Processing Speaker: Ruby Lee, - Princeton Univ. Authors:Ruby Lee - Princeton Univ., Princeton, NJ 46.4 Attacks and Countermeasures for Tamper-Resistant Embedded Hardware Devices Speaker: Paul Kocher, - Cryptography Research, Inc. Authors:Paul Kocher - Cryptography Research, Inc., San Francisco, CA ********************************************************************************** Session: 47 | Title: Leakage Power Optimization Day: Thursday June 10 2004 Time: 2:00 to 4:00 | RM : 6B Chair: Farid N. Najm - Univ. of Toronto, Toronto , ON Organizers: Enrico Macii, Naehyuck Chang This session presents different approaches for reducing leakage power consumption in deep submicron CMOS circuits. The papers investigate different trade-offs between gate Tox, Vdd, Vth and sizing. Also, techniques for deriving input vector control and encoding schemes for simultanous crosstalk and leakage power reduction on buses are described. 47.1 Tradeoffs between Gate Oxide Leakage and Delay for Dual Tox Circuits Speaker: Anup Kumar Sultania, - Univ. of Minnesota Authors:Anup Kumar Sultania - Univ. of Minnesota, Minneapolis, MN, , Dennis Sylvester- Univ. of Michigan, Ann Arbor, MI, , Sachin S. Sapatnekar- Univ. of Minnesota, Minneapolis, MN 47.2 Implicit Pseudo Boolean Enumeration Algorithms for Input Vector Control Speaker: Kaviraj S. Chopra, - Univ. of Arizona Authors:Kaviraj S. Chopra, , Sarma Vrudhula- Univ. of Arizona, Tucson, AZ 47.3 Statistical Optimization of Leakage Power Considering Process Variations Using Dual-Vth and Sizing Speaker: Ashish Srivastava, - Univ. of Michigan Authors:Ashish Srivastava, Dennis Sylvester, , David Blaauw- Univ. of Michigan, Ann Arbor, MI 47.4s Leakage - and Crosstalk-Aware Bus Encoding for Total Power Reduction Speaker: Harmander S. Deogun, - Univ. of Michigan Authors:Harmander S. Deogun, Rajeev R. Rao, Dennis Sylvester, , David Blaauw, - Univ. of Michigan, Ann Arbor, MI 47.5s Power Minimization Using Simultaneous Gate Sizing, Dual-Vdd, and Dual-Vth Assignment Speaker: Ashish Srivastava, - Univ. of Michigan Authors:Ashish Srivastava, Dennis Sylvester, , David Blaauw- Univ. of Michigan, Ann Arbor, MI ********************************************************************************** Session: 48 | Title: Interconnect Extraction Day: Thursday June 10 2004 Time: 2:00 to 4:00 | RM : 6C Chair: Yehia Massoud - Rice Univ., Houston, TX Organizers: Sachin S. Sapatnekar This session presents new developments in the area of 3D parasitic extraction. The first paper performs capacitance extraction under multi-dielectric environments. Next, a parasitic extractor for microelectronics, multichip modules and MEMS which combines the fast multipole method with QR matrix compression is presented. The third paper shows a method for determining inductive noise coupling. A full wave field solver for RF, analog and high-speed digital circuits is presented next. Finally, a presentation on a technique that develops closed-form expressions for distributed RC interconnects rounds out the session. 48.1 Sparse Transformations and Preconditioners for Hierarchical 3-D Capacitance Extraction with Multiple Dielectrics Speaker: Shu Yan, - Texas A&M Univ. Authors:Shu Yan, Vivek Sarin, , Weiping Shi- Texas A&M Univ., College Station, TX 48.2 A Fast Parasitic Extractor Based on Low Rank Multilevel Matrix Compression for Conductor and Dielectric Modeling in Microelectronics and MEMS Speaker: Dipanjan Gope, - Univ. of Washington Authors:Dipanjan Gope, Swagato Chakraborty, , Vikram Jandhyala- Univ. of Washington, Seattle, WA 48.3 CHIME: Coupled Hierarchical Inductance Model Evaluation Speaker: Satrajit Gupta, - Carnegie Mellon Univ. Authors:Satrajit Gupta, , Lawrence T. Pileggi- Carnegie Mellon Univ., Pittsburgh, PA 48.4s Large-Scale Full-Wave Simulation Speaker: Sharad Kapur, - Integrand Software, Inc. Authors:Sharad Kapur, , David E. Long- Integrand Software, Inc., Hoboken, NJ 48.5s Closed-Form Expressions of Distributed RLC Interconnects for Analysis of On-Chip Inductance Effects Speaker: Yuichi Tanji, - Kagawa Univ. Authors:Yuichi Tanji - Kagawa Univ., Takamatsu, Japan, , Hideki Asai- Shizuoka Univ., Hamamatsu, Japan ********************************************************************************** Session: 49 | Title: New Frontiers in Logic Synthesis Day: Thursday June 10 2004 Time: 2:00 to 4:00 | RM : 6D Chair: Jordi Cortadella - Univ. Polytechnica De Catalunya, Barcelona, Spain Organizers: Leon Stok, Steven M. Nowick The first paper presents a novel approach to delay variation tolerance through "voting structures". The second paper optimizes domino circuits by eliminating the need for full logic duplication. Multiplication by constants is an important problem in DSPs, and the third paper proposes a new dag fusion approach for sharing adders. The fourth paper describes simple heuristics for decomposing asynchronous controller specifications. The last two papers extend synthesis into the quantum domain. 49.1 Re-Synthesis for Delay Variation Tolerance Speaker: Cheng-Tao Hsieh, - National Tsing-Hua Univ. Authors:Shih-Chieh Chang, Cheng-Tao Hsieh, , Kai-Chiang Wu- National Tsing-Hua Univ., Hsinchu, Taiwan 49.2 Post-Layout Logic Optimization of Domino Circuits Speaker: Aiqun Cao, - Purdue Univ. Authors:Aiqun Cao, , Cheng-Kok Koh- Purdue Univ., West Lafayette, IN 49.3s Multiple Constant Multiplication by Time-Multiplexed Mapping of Addition Chains Speaker: Peter Tummeltshammer, - Univ. of Technology Vienna Authors:Peter Tummeltshammer - Univ. of Technology Vienna, Vienna, Austria, James C. Hoe, , Markus Pueschel- Carnegie Mellon Univ., Pittsburgh, PA 49.4s Decomposing Specifications with Concurrent Outputs to Resolve State Coding Conflicts in Asynchronous Logic Synthesis Speaker: Mark B. Josephs, - London South Bank Univ. Authors:Hemangee K. Kapoor, , Mark B. Josephs- London South Bank Univ., London, United Kingdom 49.5s A New Heuristic Algorithm for Reversible Logic Synthesis Speaker: Pawel Kerntopf, - Warsaw Univ. of Tech. Authors:Pawel Kerntopf - Warsaw Univ. of Tech., Warsaw, Poland 49.6s Quantum Logic Synthesis by Symbolic Reachability Analysis Speaker: William N. N. Hung, - Intel Corp. Authors:William N. N. Hung - Intel Corp., Hillsboro, OR, Xiaoyu Song, , Guowu Yang- Portland State Univ., Portland, OR, Jin Yang, - Intel Corp., Hillsboro, OR, , Marek Perkowski, - Portland State Univ., Portland, OR ********************************************************************************** Session: 50 | Title: Numerical Techniques for Simulation Day: Thursday June 10 2004 Time: 2:00 to 4:00 | RM : 4 Chair: Joel R. Phillips - Cadence Design Systems, Inc., San Jose, CA Organizers: Jacob K. White, Kartikeya Mayaram The five papers in this session on numerical techniques address a variety of issues in simulation. In the first paper, the problem of simulating complicated analog and RF circuits is addressed using a combination of partitioning, macromodeling, and iteration. The second paper examines the numerical stability issues associated with handling two time scale problems with multitime partial differential equation methods. The problems of predicting substrate noise in mixed signal systems is addressed in the third paper. Techniques for improving simulation efficiency is the subject of the last two short papers. The first paper of the pair exploits hierarchy to accelerate symbolic analysis and the second paper describes the latest approaches for using table models in circuit simulation. 50.1 A Frequency Relaxation Approach for Analog/RF System-Level Simulation Speaker: Xin Li, - Carnegie Mellon Univ. Authors:Xin Li, Yang Xu, Peng Li, Padmini Gopalakrishnan, , Lawrence T. Pileggi, - Carnegie Mellon Univ., Pittsburgh, PA 50.2 Robust, Stable Time-Domain Methods for Solving MPDE of Fast/Slow Systems Speaker: Ting Mei, - Univ. of Minnesota Authors:Ting Mei, , Jaijeet Roychowdhury- Univ. of Minnesota, Minneapolis, MN, Todd S. Coffey, Scott A. Hutchinson, , David M. Day, - Sandia National Laboratories, Albuquerque, NM 50.3 High-Level Simulation of Substrate Noise in High-Ohmic Substrates with Interconnect and Supply Effects Speaker: Geert Van der Plas, - IMEC Authors:Geert Van der Plas, Mustafa Badaroglu, Gerd Vandersteen, Petr Dobrovolny, Piet Wambacq, Stephane Donnay, - IMEC, Leuven, Belgium, , Georges Gielen, - Katholieke Univ. , Leuven , Belgium, , Hugo De Man, - IMEC, Leuven, Belgium 50.4s Hierarchical Approach to Exact Symbolic Analysis of Large Analog Circuits Speaker: Zhenyu Qi, - Univ. of California Authors:Sheldon Tan, Weikun Guo, , Zhenyu Qi- Univ. of California, Riverside, CA 50.5s An Essentially Non-Oscillatory (ENO) High-Order Accurate Adaptive Table Model for Device Modeling Speaker: Baolin Yang, - Cadence Design Systems, Inc. Authors:Baolin Yang, , Bruce MacGaughy- Cadence Design Systems, Inc., San Jose, CA ********************************************************************************** Session: 51 | Title: Energy and Thermal-Aware Design Day: Thursday June 10 2004 Time: 4:30 to 6:00 | RM : 6A Chair: Jihong Kim - Seoul National Univ., Seoul, Republic of Korea Organizers: Chaitali Chakrabarti, Sarma B. Vrudhula This session covers two different aspects of energy minimization in electronic systems. The first two papers investigate the limits of DVS scaling and the applicability of DVS to gate arrays. The last two papers deal with thermal modeling and the effects of temperature on Vdd and Vth. 51.1 Theoretical and Practical Limits of Dynamic Voltage Scaling Speaker: Bo Zhai, - Univ. of Michigan Authors:Bo Zhai, David Blaauw, , Dennis Sylvester- Univ. of Michigan, Ann Arbor, MI, Krisztian Flautner, - ARM Ltd., Cambridge, United Kingdom 51.2s Enabling Energy Efficiency in Via-Patterned Gate Array Devices Speaker: Reed Taylor, - Carnegie Mellon Univ. Authors:Reed Taylor - Carnegie Mellon Univ., Pittsburgh, PA, , Herman Schmit- Tabula, Inc., Mountain View, CA 51.3 Compact Thermal Modeling for Temperature-Aware Design Speaker: Wei Huang, - Univ. of Virginia Authors:Wei Huang, Mircea R. Stan, Kevin Skadron, Karthik Sankaranarayanan, Shougata Ghosh, Sivakumar Velusamy, - Univ. of Virginia, Charlottesville, VA 51.4s Simultaneous Optimization of Supply and Threshold Voltages for Low-Power and High-Performance Circuits in the Leakage Dominant Era Speaker: Sheng-Chih Lin, - Univ. of California Authors:Anirban Basu, , Sheng-Chih Lin- Univ. of California, Santa Barbara, CA, , Vineet Wason- University of California, Santa Barbara, CA, Amit Mehrotra, - Berkeley Design Automation Inc.,, Santa Clara , CA, , Kaustav Banerjee, - Univ. of California, Santa Barbara, CA ********************************************************************************** Session: 52 | Title: Noise-Tolerant Design and Analysis Techniques Day: Thursday June 10 2004 Time: 4:30 to 6:00 | RM : 6B Chair: David Blaauw - Univ. of Michigan, Ann Arbor, MI Organizers: Anirudh Devgan, Dennis Sylvester This session deals with various sources of noise, both traditional and non-traditional, and describes both analysis and design techniques to address them. The first paper proposes macromodels to capture the response of CMOS logic gates to input noise waveforms while the second work looks at multiple sources of noise in a circuit, including soft errors, to find noise-sensitive nodes. The third paper proposes a unique keeper structure in dynamic logic to boost noise immunity. The last work studies different approaches to global interconnect pipelining under process fluctuations, which can be viewed as another source of noise. 52.1 Noise Characterization of Static CMOS Gates Speaker: Rouwaida N. Kanj, - Univ. of Illinois Authors:Rouwaida N. Kanj - Univ. of Illinois, Urbana, IL, Timothy Lehner, , Bhavna Agrawal- IBM Corp., Hopewell Junction, NY, Elyse Rosenbaum, - Univ. of Illinois, Urbana, IL 52.2 A Scalable Soft Spot Analysis Methodology for Compound Noise Effects in Nano-Meter Circuits Speaker: Chong Zhao, - Univ. of California at San Diego Authors:Chong Zhao, Xiaoliang Bai, , Sujit Dey- Univ. of California at San Diego, La Jolla, CA 52.3s A Novel Technique to Improve Noise Immunity of CMOS Dynamic Logic Circuits Speaker: Pinaki Mazumder, - Univ. of Michigan Authors:Li Ding, , Pinaki Mazumder- Univ. of Michigan, Ann Arbor, MI 52.4s Statistical Timing Analysis in Sequential Circuit for On-Chip Global Interconnect Pipelining Speaker: Lizheng Zhang, - Univ. of Wisconsin Authors:Lizheng Zhang, , Yuhen Hu- Univ. of Wisconsin, Madison, WI, , Charlie Chung-Ping Chen- National Taiwan Univ., Taipei, Taiwan ********************************************************************************** Session: 53 | Title: New Tools and Methods for Future Embedded SoC Day: Thursday June 10 2004 Time: 4:30 to 6:00 | RM : 6C Chair: Giovanni De Micheli - Stanford Univ., Stanford, CA Organizers: Marcello Coppola, Pai H. Chou This session illustrates the wide range and variety of design tools and methodologies for future embedded systems. The first paper is unique in reporting actual measured design process results and pitfalls for a video encoder case study. The second paper reports on an innovative new tool which automates large parts of Network-on-Chip design. This is followed by two short papers, one of which looks again at the whole concept of RISC to generate extreme application oriented processors. The final paper addresses the use of domain specific languages as a new entry point for embedded design through the use of a networking application. 53.1 Debugging HW/SW Interface for MPSoC: Video Encoder System Design Case Study Speaker: Mohamed-Wassim Youssef, - TIMA Lab. Authors:Mohamed-Wassim Youssef, Sungjoo Yoo, Arif Sasongko, Yanick Paviot, , Ahmed A. Jerraya, - TIMA Lab., Grenoble, France 53.2 SUNMAP: A Tool for Automatic Topology Selection and Generation for NoCs Speaker: Srinivasan Murali, - Stanford Univ. Authors:Srinivasan Murali, , Giovanni De Micheli- Stanford Univ., Stanford, CA 53.3s FITS: Framework-Based Instruction-Set Tuning Synthesis for Embedded Application Specific Processors Speaker: Allen Cheng, - Univ. of Michigan Authors:Allen Cheng - Univ. of Michigan, Ann Arbor, MI, , Gary Tyson- Florida State Univ., Tallahassee, FL, , Trevor Mudge- Univ. of Michigan, Ann Arbor, MI 53.4s Mapping a Domain Specific Language to a Platform FPGA Speaker: Chidamber Kulkarni, - Xilinx, Inc. Authors:Chidamber Kulkarni, , Gordon Brebner- Xilinx, Inc., San Jose, CA, , Graham Schelle- Univ. of Colorado, Boulder, CO ********************************************************************************** Session: 54 | Title: New Scan-Based Test Techniques Day: Thursday June 10 2004 Time: 4:30 to 6:00 | RM : 6D Chair: Bernd Koenemann - Cadence Design Systems, Inc., San Jose, CA Organizers: Erik Jan Marinissen, Seiji Kajihara All papers in this session give new solutions on scan-based testing. The first paper considers generating tests for scan circuits that ensure that the test only uses funtionally reachable states. This is done in order to avoid reducing yield caused by tests that operate the circuits in non-functional mode. The other two papers describe new architectures for scan-based BIST which will target flexible features and simple implementation, respectively. The last paper presents a test compression method for multiple scan design. 54.1 On the Generation of Scan-Based Test Sets with Reachable States for Testing under Functional Operation Conditions Speaker: Irith Pomeranz, - Purdue Univ. Authors:Irith Pomeranz - Purdue Univ., West Lafayette, IN 54.2 Scalable Selector Architecture for X-Tolerant Deterministic BIST Speaker: Peter Wohl, - Synopsys, Inc. Authors:Peter Wohl, John A. Waicukauski, , Sanjay Patel- Synopsys, Inc., Beaverton, OR 54.3s Scan-BIST Based on Transition Probabilities Speaker: Irith Pomeranz, - Purdue Univ. Authors:Irith Pomeranz - Purdue Univ., West Lafayette, IN 54.4s Combining Dictionary Coding and LFSR Reseeding for Test Data Compression Speaker: Xiaoyun Sun, - Univ. of Minnesota Authors:Xiaoyun Sun, Larry Kinney, , Bapiraju Vinnakota- Univ. of Minnesota, Minneapolis, MN ********************************************************************************** Session: 55 | Title: CAD for Reconfigurable Computing Day: Thursday June 10 2004 Time: 4:30 to 6:00 | RM : 4 Chair: Jason Cong - Magma Design Automation, Inc., Los Angeles, CA Organizers: Jens Palsberg, Scott Hauck By combining the fast reconfiguration of microprocessors with the high-performance of hardware, FPGAs open up new challenges to the CAD designer. This session considers fast algorithms for reconfigurable computing as well as operating systems support for such systems. 55.1 Virtual Memory Window for Application-Specific Reconfigurable Coprocessors Speaker: Miljan Vuletic, - Swiss Federal Institute of Tech. Authors:Miljan Vuletic, Laura Pozzi, , Paolo Ienne- Swiss Federal Institute of Tech., Lausanne, Switzerland 55.2 Dynamic FPGA Routing for Just-in-Time FPGA Compilation Speaker: Roman Lysecky, - Univ. of California Authors:Roman Lysecky, Frank Vahid, , Sheldon X.-D. Tan- Univ. of California, Riverside, CA 55.3 An Efficient Algorithm for Finding Empty Space for Online FPGA Placement Speaker: Manish Handa, - Univ. of Cincinnati Authors:Manish Handa, , Ranga Vemuri- Univ. of Cincinnati, Cincinnati, OH **********************************************************************************