Session: 1 | Title: PANEL: Differentiate and Deliver: Leveraging Your Design and Manufacturing Partners from Product Concept to Production Day: Tuesday June 14 2005 Time: 10:30 to 12:00 | RM : 207ABC Chair: Jay Vleeschhouwer - Merrill Lynch, New York, NY Organizers: Rich Goldman, David Park Semiconductor companies face many key questions when developing a new product: Is there a serviceable market need? Do I have a product idea that is unique and differentiated? What parts of my design do I "make" vs. "buy"? What is the right process node for the first implementation? More so than ever before, the answers to these questions are influenced by the EDA, IP and Foundry partners with whom the semiconductor companies collaborate. Collectively, these companies must align their own core competencies with those of the semiconductor company to create a product with the optimal combination of performance, price, and time-to-market. In this panel, the CEOs of the three major EDA vendors, along with peers from the IP and manufacturing areas, discuss these fundamental questions as well as the challenges of working together to help customers successfully bring new products to market. 1.1 PANEL: Differentiate and Deliver: Leveraging your Partners from Product Concept to Production (CEO Panel) Speaker: Warren East, - CEO, ARM Ltd.Michael J. Fister, - CEO, Cadence Design Systems, Inc.Walden C. Rhines, - CEO, Mentor Graphics Corp.Jackson Hu, - CEO, United Microelectronics Corp. Authors: ********************************************************************************** Session: 2 | Title: Special Session: Error-Tolerant Design Day: Tuesday June 14 2005 Time: 10:30 to 12:00 | RM : 210CD Chair: Sarma Vrudhula - Univ. of Arizona, Tucson, AZ Organizers: Krishnendu Chakrabarty, Sarma Vrudhula Industry presentations on various aspects of soft errors - causes, impacts, and mitigation. Highlight conclusions of upcoming workshop on soft errors. 2.1 Logic Soft Errors in sub-65 nm Technologies: Design and CAD Challenges Speaker: Subhasish Mitra, - Intel Corp. Authors:Subhasish Mitra, Tanay Karnik, Norbert Seifert, , Ming Zhang, - Intel Corp., Folsom, CA 2.2 SEU-Tolerant Device, Circuit and Processor Design Speaker: Bill Heidergott, - General Dynamics Decision Systems Authors:Bill Heidergott - General Dynamics Decision Systems, Scottsdale, AZ 2.3 System Effects of Transient Particle Induced Upsets Speaker: Pia N. Sanda, - IBM Corp. Authors:Pia N. Sanda, Ethan H. Cannon, Scott Swaney, , David M. Cole, - IBM Corp., White Plains, NY ********************************************************************************** Session: 3 | Title: Microarchitecture-Level Power Analysis and Optimization Techniques Day: Tuesday June 14 2005 Time: 10:30 to 12:00 | RM : 210AB Chair: Mary Jane Irwin - Penn State Univ., University Park, PA Organizers: Sujit Dey, Trevor Mudge This session covers various topics related to energy optimization and modeling at the microarchitecture-architecture boundary. 3.1 Variability and Energy Awareness: A Microarchitecture-Level Perspective Speaker: Diana Marculescu, - Carnegie Mellon Univ. Authors:Diana Marculescu, , Emil Talpes- Carnegie Mellon Univ., Pittsburgh, PA 3.2 Energy-Efficient Physically Tagged Caches for Embedded Processors with Virtual Memory Speaker: Peter D. Petrov, - Univ. of Maryland Authors:Peter D. Petrov - Univ. of Maryland, College Park, MD, Daniel Tracy, , Alex Orailoglu- Univ. of California at San Diego, La Jolla, CA 3.3s Hybrid Simulation for Embedded Software Energy Estimation Speaker: Anish Muttreja, - Princeton Univ. Authors:Anish Muttreja - Princeton Univ., Princeton, NJ, Anand Raghunathan, , Srivaths Ravi- NEC Laboratories America, Princeton, NJ, Niraj K. Jha, - Princeton Univ., Princeton, NJ 3.4s Cooperative Multithreading on Embedded Multiprocessor Architectures Enables Energy-Scalable Design Speaker: Bo-Cheng Charles Lai, - Univ. of California Authors:Patrick R. Schaumont, , Bo-Cheng Charles Lai- Univ. Of California, Los Angeles, CA, , Wei Qin- Boston Univ., Boston, MA, Ingrid Verbauwhede, - Univ. Of California, Los Angeles, CA ********************************************************************************** Session: 4 | Title: Leakage Analysis and Optimization Day: Tuesday June 14 2005 Time: 10:30 to 12:00 | RM : 209AB Chair: Yu Cao - Arizona State University, Tempe, AZ Organizers: Tanay Karnik This session presents several different techniques for leakage analysis and optimization. The first paper presents a technique for total power reduction using gate sizing and multiple VT. The second paper describes a technique for reducing the short-circuit current when MTCMOS circuits transition from sleep to active state. The third paper dynamically determines the optimal reverse body bias for leakage control. The last paper shows a new technique of gate replacement for leakage reduction. 4.1 Total Power Reduction in CMOS Circuits via Gate Sizing and Multiple Threshold Voltages Speaker: Feng Gao, - Univ. of Michigan Authors:Feng Gao, , John P. Hayes- Univ. of Michigan, Ann Arbor, MI 4.2 An Effective Power Mode Transition Technique in MTCMOS Circuits Speaker: Afshin Abdollahi, - Univ. of Southern California Authors:Afshin Abdollahi - Univ. of Southern California, Los Angeles, CA, , Farzan Fallah- Fujitsu Labs of America, Inc., Sunnyvale, CA, , Massoud Pedram- Univ. of Southern California, Los Angeles, CA 4.3s A Self-adjusting Scheme to Determine the Optimum RBB by Monitoring Leakage Currents Speaker: Nikhil Jayakumar, - Texas A&M Univ. Authors:Nikhil Jayakumar - Texas A&M Univ., College Station, TX, , Sandeep Dhar- National Semiconductor Corp., Longmont, CO, , Sunil Khatri- Texas A&M Univ., College Station, TX 4.4s Enhanced Leakage Reduction Technique by Gate Replacement Speaker: Lin Yuan, - Univ. of Maryland Authors:Lin Yuan, , Gang Qu- Univ. of Maryland, College Park, MD ********************************************************************************** Session: 5 | Title: Analog Macromodeling Day: Tuesday June 14 2005 Time: 10:30 to 12:00 | RM : 208AB Chair: Georges Gielen - Katholieke Universiteit, Leuven, Belgium Organizers: Geert Van Der Plas, Helmut Graeb This session presents recent advances in automatic generation of macromodels for analog circuits. The first paper shows piecewise polynomial nonlinear modeling of I/O buffers. The second paper describes a new method to create a structural model by decoupling internal feedback loops. The third paper presents a new response surface modeling technique that combines support vector machines and dynamic learning schemes. 5.1 Automated Nonlinear Macromodeling of Output Buffers for High-Speed Digital Applications Speaker: Ning Dong, - Univ. of Minnesota Authors:Ning Dong, , Jaijeet Roychowdhury- Univ. of Minnesota, Minneapolis, MN 5.2 Systematic Development of Analog Circuit Structural Macromodels Through Behavioral Model Decoupling Speaker: Ying Wei, - State Univ. of New York Authors:Ying Wei, , Alex Doboli- State Univ. of New York, Stony Brook, NY 5.3 A Combined Feasibility and Performance Macromodel for Analog Circuits Speaker: Mengmeng Ding, - Univ. of Cincinnati Authors:Mengmeng Ding, , Ranga Vemuri- Univ. of Cincinnati, Cincinnati, OH ********************************************************************************** Session: 6 | Title: PANEL: ESL: Tales From the Trenches Day: Tuesday June 14 2005 Time: 2:00 to 4:00 | RM : 207ABC Chair: David Maliniak - Electronic Design, Paramus, NJ Organizers: Francine Bacchini ESL design has arrived - but can ESL provide the bridge from systems to silicon? Hear from real-world designers as to what works, what doesn’t, and what the gaps are in the methodology and tool offerings. Panelists from military/aerospace, storage area networks (SAN), wireless communications, and consumer electronics industry segments will share their experiences, lessons learned, and further needs. 6.1 PANEL: ESL: Tales from the Trenches Speaker: Terry Doherty, - Emulex Corp.Peter McShane, - Northrop Grumman Space TechnologySuhas A. Pai, - QUALCOMM IncorporatedSriram Sundararajan, - Texas Instruments, Inc.Soo-Kwan Eo, - Samsung Electronics Authors: ********************************************************************************** Session: 7 | Title: Statistical Timing Analysis Day: Tuesday June 14 2005 Time: 2:00 to 4:00 | RM : 210CD Chair: Vinod Kariat - Cadence Design Systems, Inc., San Jose, CA Organizers: Joel Phillips, Kenneth Shepard This session describes new advances in statistical static timing analysis. In particular, these papers describe techniques to handle nonlinear and non-Gaussian parameters and preserve correlations, including both process dependence and reconvergent circuit paths. 7.1 Parameterized Block-Based Statistical Timing Analysis with Non-Gaussian Parameters and Nonlinear Delay Functions Speaker: Hongliang Chang, - Univ. of Minnesota Authors:Hongliang Chang - Univ. of Minnesota, Minneapolis, MN, Vladimir Zolotov, Chandu Visweswariah, , Sambasivan Narayan, - IBM Corp., Essex Jct., VT 7.2 Correlation-Aware Statistical Timing Analysis with Non-Gaussian Delay Distributions Speaker: Yaping Zhan, - Carnegie Mellon Univ. Authors:Yaping Zhan, Andrzej J. Strojwas, Xin Li, , Lawrence T. Pileggi, - Carnegie Mellon Univ., Pittsburgh, PA, David Newmark, Mahesh Sharma, - Advanced Micro Devices, Inc., Austin, TX 7.3 Correlation-Preserved Non-Gaussian Statistical Timing Analysis with Quadratic Timing Model Speaker: Lizheng Zhang, - Univ. of Wisconsin Authors:Lizheng Zhang, Weijen Chen, Yuhen Hu, , John A. Gubner, - Univ. of Wisconsin, Madison, WI, , Charlie Chung-Ping Chen, - National Taiwan Univ., Taipei , Taiwan 7.4 A General Framework for Accurate Statistical Timing Analysis Considering Correlations Speaker: Vishal Khandelwal, - Univ. of Maryland Authors:Vishal Khandelwal, , Ankur Srivastava- Univ. of Maryland, College Park, MD ********************************************************************************** Session: 8 | Title: Embedded Software Day: Tuesday June 14 2005 Time: 2:00 to 4:00 | RM : 210AB Chair: Rainer Leupers - RWTH Aachen Univ., Aachen , Germany Organizers: Lothar Thiele With increasing chip density and application complexity, embedded systems now include multiple processors and sophisticated memory hierarchies (caches, multiple memory banks, etc). It is imperative that embedded software fully exploits parallelism and uses the memory hierarchy to increase performance and reduce power consumption. At the same time, the applications increasingly include real-time constraints, and therefore, task scheduling and run-time estimation techniques are becoming mandatory. 8.1 Locality-Conscious Workload Assignment for Array-Based Computations in MPSOC Architectures Speaker: Feihui Li, - Pennsylvania State Univ. Authors:Feihui Li, , Mahmut Kandemir- Pennsylvania State Univ., University Park, PA 8.2s Automatic Scenario Detection for Improved WCET Estimation Speaker: Valentin S. Gheorghita, - Eindhoven Univ. of Technology Authors:Valentin S. Gheorghita, Sander Stuijk, Twan Basten, , Henk Corporaal, - Eindhoven Univ. of Technology, Eindhoven, Netherlands 8.3 Memory Access Optimization Through Combined Code Scheduling, Memory Allocation, and Array Binding in Embedded System Design Speaker: Taewhan Kim, - Seoul National Univ. Authors:Jungeun Kim - KAIST, Daejeon, South Korea, , Taewhan Kim- Seoul National Univ., Seoul, South Korea 8.4 Dynamic Slack Reclamation with Procrastination Scheduling in Real-Time Embedded Systems Speaker: Ravindra R. Jejurikar, - Univ. of California Authors:Ravindra R. Jejurikar - Univ. of California, Irvine, CA, , Rajesh Gupta- Univ. of California at San Diego, La Jolla, CA ********************************************************************************** Session: 9 | Title: Advances in Design-for-Testability Methods Day: Tuesday June 14 2005 Time: 2:00 to 4:00 | RM : 209AB Chair: Tom Williams - Synopsys, Inc., Boulder, CO Organizers: Erik Jan Marinissen, Patrick Girard This session presents novel scan-based techniques that improve test quality, reduce test costs, and ensure secure testable ICs. 9.1 Response Compression with Unlimited Number of Unknowns Using a New LFSR Architecture Speaker: Erik H. Volkerink, - Agilent Technologies, Inc. Authors:Erik H. Volkerink - Agilent Technologies, Inc., San Jose, CA, , Subhasish Mitra- Intel Corp., Folsom, CA 9.2 Multi-Frequency Wrapper Design and Optimization for Embedded Cores Under Average Power Constraints Speaker: Qiang Xu, - McMaster Univ. Authors:Qiang Xu, , Nicola Nicolici- McMaster Univ., Hamilton, Canada, , Krishnendu Chakrabarty- Duke Univ., Durham, NC 9.3 N-Detection Under Transparent-Scan Speaker: Irith Pomeranz, - Purdue Univ. Authors:Irith Pomeranz - Purdue Univ., West Lafayette, IN 9.4 Secure Scan: A Design-for-Test Architecture for Crypto Chips Speaker: Bo Yang, - Polytechnic Univ. Authors:Bo Yang - Polytechnic Univ., Brooklyn, NY, , Kaijie Wu- Univ. of Illinois, Chicago, IL, , Ramesh Karri- Polytechnic Univ., Brooklyn, NY ********************************************************************************** Session: 10 | Title: Advances in Boundary Element Methods for Parasitic Extraction Day: Tuesday June 14 2005 Time: 2:00 to 4:00 | RM : 208AB Chair: J. Eric Bracken - Ansoft Corporation, Pittsburgh, PA Organizers: Yehea Ismail This session presents advances in parasitic extraction based on boundary element methods. The first paper presents a surface-volume method for inhomogeneous substrates. The second paper presents a full-wave technique for impedance conduction over layered substrates. The third paper presents an extraction approach for spatially distributed 3D circuit models. The fourth paper presents a direct multilevel method for fast capacitance extraction, and the fifth paper presents a reordering and transformation method for accelerating capacitance extraction. 10.1 A Green Function-Based Parasitic Extraction Method for Inhomogeneous Substrate Layers Speaker: Chenggang Xu, - Oregon State Univ. Authors:Chenggang Xu - Oregon State Univ., Corvallis, OR, , Ranjit Gharpurey- Univ. of Michigan, Ann Arbor, MI, Terri Fiez, , Kartikeya Mayaram, - Oregon State Univ., Corvallis, OR 10.2 Analysis of Full-Wave Conductor System Impedance Over Substrate Using Novel Integration Techniques Speaker: Xin Hu, - Massachusetts Institute of Tech. Authors:Xin Hu, Jung Hoon Lee, Jacob White, , Luca Daniel, - Massachusetts Institute of Tech., Cambridge, MA 10.3 Spatially Distributed 3D Circuit Models Speaker: Michael Beattie, - IBM Corp. Authors:Michael Beattie, Hui Zheng, Byron Krauter, , Anirudh Devgan, - IBM Corp., Austin, TX 10.4s DiMES: Multilevel Fast Direct Solver based on Multipole Expansions for Parasitic Extraction of Massively Coupled 3D Microelectronic Structures Speaker: Dipanjan Gope, - Univ. of Washington Authors:Dipanjan Gope, Indranil Chowdhury, , Vikram Jandhyala- Univ. of Washington, Seattle, WA 10.5s ICCAP: A Linear Time Sparse Transformation and Reordering Algorithm for Three-Dimensional BEM Capacitance Extraction Speaker: Rong Jiang, - Univ. of Wisconsin Authors:Rong Jiang, , Charlie Chung-Ping Chen- Univ. of Wisconsin, Madison, WI, , Yi-Hoa Chang- Natl. Taiwan Univ., Taipei, Taiwan ********************************************************************************** Session: 11 | Title: PANEL: DFM Rules! Day: Tuesday June 14 2005 Time: 4:30 to 6:30 | RM : 207ABC Chair: Naveed Sherwani - Open-Silicon, Sunnyvale, CA Organizers: Susan Lippincott Mack At 90 nm, yields appeared unpredictable. Two chips designed with the same methodology and design rules deliver completely different manufacturing yields. This panel will discuss the reasons for this phenomenon and talk about future trends in DFM that will need to be addressed for success below 100 nm. 11.1 PANEL: DFM Rules! Speaker: Atul Sharan, - Clear Shape Technologies, Inc.Alex Alexanian, - Ponte Solutions, Inc.Harold Lehon, - KLA-Tencor Corp.Peter Rabkin, - Xilinx, Inc.Carlo Guardiani, - PDF Solutions, Inc. Authors: ********************************************************************************** Session: 12 | Title: Recent Advances in Signal Integrity Day: Tuesday June 14 2005 Time: 4:30 to 6:30 | RM : 210CD Chair: Eli Chiprout - Intel Corp., Chandler, AZ Organizers: Dusan Petranovic, Lei He This session describes advances in a range of topics in the signal integrity area. The first paper discusses an efficient approach to budgeting decoupling capacitance in order to improve power grid integrity. The next two papers discuss clock network optimization using register placement and a novel opposite-phase scheme to reduce peak current demands, respectively. The next paper details an effective capacitance model for fast noise analysis. The final paper presents an approach to selectively inserting hardened flip-flops in a general circuit to improve robustness while maintaining timing/area constraints. 12.1 Partitioning-Based Approach to Fast On-Chip Decap Budgeting and Minimization Speaker: Hang Li, - Univ. of California Authors:Hang Li, Zhenyu Qi, , Sheldon Tan- Univ. of California, Riverside, CA 12.2 Navigating Registers in Placement for Clock Network Minimization Speaker: Yongqiang Lu, - Tsinghua Univ. Authors:Yongqiang Lu - Tsing-Hua Univ., Beijing, China, , C. N. Sze- Texas A&M Univ., College Station, TX, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, - Tsing-Hua Univ., Beijing, China, , Jiang Hu, - Texas A&M Univ., College Station, TX 12.3s Minimizing Peak Current via Opposite-Phase Clock Tree Speaker: Shih-Hsu Huang, - Chung Yuan Christian Univ. Authors:Yow-Tyng Nieh, , Shih-Hsu Huang- Chung Yuan Christian Univ., Chung Li, Taiwan, , Sheng-Yu Hsu- Industrial Technology Research Institute, Hsin Chu, Taiwan 12.4s A Noise-Driven Effective Capacitance Method With Fast Embedded Noise Rule Calculation for Functional Noise Analysis Speaker: Haihua Su, - IBM Corp. Authors:Haihua Su, David J. Widiger, Chandramouli V. Kashyap, Frank Y. Liu, , Byron Krauter, - IBM Corp., Austin, TX 12.5 Constraint-Aware Robustness Insertion for Optimal Noise-Tolerance Enhancement in Digital VLSI Circuits Speaker: Chong Zhao, - Univ. of California at San Diego Authors:Chong Zhao, Yi Zhao, , Sujit Dey- Univ. of California at San Diego, La Jolla, CA ********************************************************************************** Session: 13 | Title: Physical Considerations in High-Level Synthesis Day: Tuesday June 14 2005 Time: 4:30 to 6:30 | RM : 210AB Chair: Steven M. Burns - Intel Corp., Portland, OR Organizers: Gila Kamhi, Reinaldo Bergamaschi This session brings together five interesting papers using physical considerations (floorplanning and layout) in high-level synthesis. The first two papers deal with temperature and power issues in high-level design; the third paper considers floorplanning together with high-level synthesis for area and power optimization; the fourth paper deals with encoding techniques for power reduction; and the fifth paper uses specific layout techniques for watermarking. 13.1 Temperature-Aware Resource Allocation and Binding in High-Level Synthesis Speaker: Rajarshi Mukherjee, - Northwestern Univ. Authors:Rajarshi Mukherjee, Seda Ogrenci Memik, , Gokhan Memik- Northwestern Univ., Evanston, IL 13.2 Leakage Power Optimization with Dual-Vth Library in High-Level Synthesis Speaker: Hai Zhou, - Northwestern Univ. Authors:Xiaoyong Tang - Magma Design Automation, Inc., Santa Clara, CA, , Hai Zhou- Northwestern Univ., Evanston, IL, , Prith Banerjee- Univ. of Illinois, Chicago, IL 13.3 Incremental Exploration of the Combined Physical and Behavioral Design Space Speaker: Zhenyu Gu, - Northwestern Univ. Authors:Zhenyu Gu, Jia Wang, Robert P. Dick, , Hai Zhou, - Northwestern Univ., Evanston, IL 13.4s Sign Bit Reduction Encoding For Low Power Applications Speaker: Zainolabedin Navabi, - Univ. of Tehran Authors:Mohsen Saneei, Ali Afzali-Kusha, , Zainolabedin Navabi- Univ. of Tehran, Tehran, Iran 13.5s A Watermarking System for IP Protection by a Post-Layout Incremental Router Speaker: Tingyuan Nie, - Kochi Univ. Authors:Tingyuan Nie, Tomowo Kisaka, , Masahiko Toyonaga- Kochi Univ., Kochi, Japan ********************************************************************************** Session: 14 | Title: Architectures for Cryptography and Security Applications Day: Tuesday June 14 2005 Time: 4:30 to 6:30 | RM : 209AB Chair: Anand Raghunathan - NEC-Labs America, Inc., Princeton, NJ Organizers: Adam Donlin, Peter Marwedel Security has been proposed as a new design dimension for embedded systems. The papers in this session consider the issue of secure embedded hardware and architectures. The first two papers discuss how embedded systems can be secured against differential power analysis. The third and fourth papers address security for network enabled embedded systems by describing a pattern matching co-processor to assist in intrusion detection and an encryption core for wireless communications. The last paper in the session addresses security at the human interface to the embedded system with a hardware-accelerated fingerprint co-processor. 14.1 A Side-Channel Leakage Free Co-processor IC in .18um CMOS for Embedded AES-Based Cryptographic and Biometric Processing Speaker: Kris Tiri, - Univ. of California Authors:Kris Tiri, David Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin YangPatrick R. Schaumont, , Ingrid Verbauwhede, - Univ. of California, Los Angeles, CA 14.2 Simulation Models for Side-Channel Information Leaks Speaker: Kris Tiri, - Univ. of California Authors:Kris Tiri, , Ingrid Verbauwhede- Univ. of California, Los Angeles, CA 14.3 A Pattern Matching Co-processor for Network Security Speaker: Young H. Cho, - Univ. of California Authors:Young H. Cho, , William H. Mangione-Smith- Univ. of California, Los Angeles, CA 14.4s A High Performance Encryption Core for Wireless 3G Networks Speaker: Rene Cumplido, - INAOE Authors:Tomas Balderas, , Rene Cumplido- INAOE, Mexico 14.5s Efficient and Secure Fingerprint-Based User Authentication for Embedded Systems Speaker: Pallav Gupta, - Princeton Univ. Authors:Pallav Gupta - Princeton Univ., Princeton, NJ, Srivaths Ravi, , Anand Raghunathan- NEC-Labs America, Inc., Princeton, NJ, Niraj K. Jha, - Princeton Univ., Princeton, NJ ********************************************************************************** Session: 15 | Title: Performance, Energy, and Fault-Tolerance Considerations for MPSoC Designs Day: Tuesday June 14 2005 Time: 4:30 to 6:30 | RM : 208AB Chair: Gerd Ascheid - RWTH Aachen Univ., Aachen, Germany Organizers: Radu Marculescu, Rainer Leupers For hardware-software co-design, the evaluation and fine tuning of the architecture, software, and individual components represent a critical step toward matching the tight design constraints and providing quick feedback to system designers. The system-level papers selected for this session cover a broad range of techniques and optimization metrics which can support various architectures and platforms. The first three papers deal with early analytical and simulation-based performance evaluation and cost-effective implementation. The last two papers present possible energy/fault-tolerance trade-offs relevant to both computation and communication infrastructure design. By attending this session the audience will get a deep insight into the most stringent issues that system designers have to deal with in order to design tomorrow's complex MPSoCs. 15.1 Approximate VCCs: A New Characterization of Multimedia Workloads for System-level MpSoC Design Speaker: Yanhong Liu, - National Univ. of Singapore Authors:Yanhong Liu, Samarjit Chakraborty, , Wei Tsang Ooi- National Univ. of Singapore, Singapore 15.2 Modular Domain-specific Implementation and Exploration Framework for Embedded Software Platforms. Speaker: Christian Sauer, - Infineon Tech. Authors:Christian Sauer, Matthias C. Gries, , Soeren Sonntag- Infineon Tech., Munich, Germany 15.3 Simulation Based Deadlock Analysis for System Level Designs Speaker: Xi Chen, - Univ. of California Authors:Xi Chen, Abhijit Davare, Harry Hsieh, , Alberto Sangiovanni-Vincentelli, - Univ. of California, Berkeley, CA, , Yosinori Watanabe, - Cadence Berkeley Labs, Berkeley, CA 15.4s Fault and Energy-Aware Communication Mapping with Guaranteed Latency for Applications Implemented on NoC Speaker: Sorin Manolache, - Linkoping Univ. Authors:Sorin Manolache, Petru Eles, , Zebo Peng- Linkoping Univ., Linköping, Sweden 15.5s High Performance Computing on Fault-Prone Nanotechnologies: Novel Microarchitecture Techniques Exploiting Reliability-Delay Trade-offs Speaker: Elias Mizan, - Univ. of Texas Authors:Andrey Zykov, Elias Mizan, Margarida Jacome, Gustavo de Veciana, , Ajay Subramanian, - Univ. of Texas, Austin, TX ********************************************************************************** Session: 16 | Title: Special Session: Closing the Power Gap Between ASIC and Custom Day: Wednesday June 15 2005 Time: 8:30 to 10:00 | RM : 207ABC Chair: Barry Pangrle - Synopsys, Inc., Mountain View, CA Organizers: Dennis Sylvester This session is balanced to provide a mixture of custom and ASIC perspectives, as well as to provide a mixture of academic and industrial perspectives. Similar sessions (focused on speed rather than power) at DAC 2000 and 2001 were well attended. The work of the presenters has refocused on power, and there are sufficient results now to give a mature perspective. 16.1 Closing the Power Gap between ASIC and Custom: An ASIC Perspective Speaker: David G. Chinnery, - Univ. of California Authors:David G. Chinnery, , Kurt Keutzer- Univ. of California, Berkeley, CA 16.2 Explaining the Gap between ASIC and Custom Power: A Custom Perspective Speaker: Andrew Chang, - Cadence Design Systems, Inc. Authors:Andrew Chang - Cadence Design Systems, Inc., San Jose, CA, , William J. Dally- Stanford Univ., Stanford, CA 16.3 Keeping Hot Chips Cool Speaker: Ruchir Puri, - IBM Corp. Authors:Ruchir Puri, Leon Stok, , Subhrajit Bhattacharya- IBM Corp., Yorktown Heights, NY ********************************************************************************** Session: 17 | Title: PANEL: My Giga Hertz: Does Yours? Day: Wednesday June 15 2005 Time: 8:30 to 10:00 | RM : 210CD Chair: Rick Merritt - EE Times, San Mateo, CA Organizers: Phil Dworsky Nearly every SoC will have an interface that relies on high-speed interconnect technology. Today, designers are "comfortable" with connections that run at 100's of megahertz, but making the transition to standards like PCI Express will instantly bring them into the GHz range, introducing a whole new universe of design challenges. Designers will need to understand the challenges they'll face as well as what to look for in the solutions they acquire to add this kind of technology to their SoCs. 17.1 PANEL: My Giga Hertz: Does Yours? Speaker: John F. D'Ambrosia, - Tyco Electronics Corp.Adam Healey, - Agere Systems, Inc.Boris Litinsky, - RF Micro Devices, Inc.John T. Stonick, - Synopsys, Inc.Joe Abler, - IBM Corp. Authors: ********************************************************************************** Session: 18 | Title: Wireless Session: Wireless Driving Innovations in Design Methodology Day: Wednesday June 15 2005 Time: 8:30 to 10:00 | RM : 210AB Chair: Ingrid Verbauwhede - Univ. of California and K.U. Leuven, Los Angeles, CA Organizers: Ingrid Verbauwhede The complexity of wireless systems together with the resource constraints (area, power, cost) requires the use of advanced design methods. In this session three examples are given. The first paper describes how low cost, reliable antennas can be built on printed circuit boards using a combination of 2.5D and 3D EM simulators with PCB design tools. The second paper describes design steps used to design a parametrizable IP core for a wireless channel estimation engine. The third paper describes cross-layer system design methods to combine low power with flexibility in radios. 18.1 Design Methodology for Wireless Nodes with Printed Antennas Speaker: Jean-Samuel Chenard, - McGill Univ. Authors:Jean-Samuel Chenard, Chun Yiu Chu, Zeljko Zilic, , Milica Popovic, - McGill Univ., Montreal, Canada 18.2 MP Core: Algorithm and Design Techniques for Efficient Channel Estimation in Wireless Applications Speaker: Yan Meng, - Univ. of California Authors:Yan Meng, Andrew P. Brown, Ronald A. Iltis, Ryan Kastner, Timothy Sherwood, Hua Lee, - Univ. of California, Santa Barbara, CA 18.3 From Myth to Methodology: Cross-Layer Design for Energy-Efficient Wireless Communication Speaker: Wolfgang Eberle, - IMEC Authors:Wolfgang Eberle, Francky Catthoor, Bruno Bougard, , Sofie Pollin, - IMEC, Leuven, Belgium ********************************************************************************** Session: 19 | Title: Statistical Optimization and Manufacturability Day: Wednesday June 15 2005 Time: 8:30 to 10:00 | RM : 209AB Chair: Chandramouli Kashyap - IBM Corp., Austin, TX Organizers: Sani Nassif, Vivek De The impact of variations on performance and power is becoming worse with technology scaling. The first three papers describe sizing algorithms that account for variations and perform statistical design optimizations to improve yield under power and timing constraints. The last paper describes alogortihms to avoid and fix antenna effect problems for yield improvement. 19.1 An Efficient Algorithm for Statistical Minimization of Total Power Under Timing Yield Constraints Speaker: Michael Orshansky, - Univ. of Texas Authors:Murari Mani - Univ. of Texas, Austin, TX, , Anirudh Devgan- Magma Design Automation, Inc., Austin, TX, , Michael Orshansky- Univ. of Texas, Austin, TX 19.2 Robust Gate Sizing by Geometric Programming Speaker: Jaskirat Singh, - Univ. of Minnesota Authors:Jaskirat Singh, Vidyasagar Nookala, Zhi-Quan Luo, , Sachin S. Sapatnekar, - Univ. of Minnesota, Minneapolis, MN 19.3s Circuit Optimization Using Statistical Static Timing Analysis Speaker: Aseem Agarwal, - Univ. of Michigan Authors:Aseem Agarwal - Univ. of Michigan, Ann Arbor, MI, , Vladimir Zolotov- IBM Corp., Yorktown Heights, NY, David Blaauw, , Kaviraj S. Chopra, - Univ. of Michigan, Ann Arbor, MI 19.4s An Optimal Jumper Insertion Algorithm for Antenna Effect Avoidance/Fixing Speaker: Bor-Yiing Su, - National Taiwan Univ. Authors:Bor-Yiing Su, , Yao-Wen Chang- National Taiwan Univ., Taipei, Taiwan ********************************************************************************** Session: 20 | Title: Application Specific Architecture Design Tools Day: Wednesday June 15 2005 Time: 8:30 to 10:00 | RM : 208AB Chair: Nikil Dutt - Univ. of California, Irvine, CA Organizers: Joachim Gerlach, Margarida Jacome This session addresses tools and methods to support design space exploration and specialization of embedded computing systems, critical towards achieving increasingly stringent performance and energy efficiency requirements. The first paper proposes an application source code micro-profiling approach for fast and accurate characterization of embedded applications during ASIP design. The second paper proposes physically-aware methods for simultaneous partitioning, scheduling, and placement of tasks on dynamically reconfigurable architectures. The third and fourth papers address fast early simulation taking advantage of evaluation reuse schemes and virtual synchronization techniques. 20.1 Fine-grained Application Source Code Profiling for ASIP Design Speaker: Kingshuk Karuri, - RWTH Aachen Univ. Authors:Kingshuk Karuri, Mohammad Al Faruque, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, - RWTH Aachen Univ., Aachen, Germany 20.2 Physically-aware HW-SW Partitioning for reconfigurable architectures with partial dynamic reconfiguration Speaker: Sudarshan Banerjee, - Univ. of California Authors:Sudarshan Banerjee, Elaheh Bozorgzadeh, , Nikil Dutt- Univ. of California, Irvine, CA 20.3s Performance Simulation Modeling for Fast Evaluation of Pipelined Scalar Processor by Evaluation Reuse Speaker: Ho Young Kim, - KAIST Authors:Ho Young Kim, , Tag Gon Kim- KAIST, Daejeon, South Korea 20.4s Trace-Driven HW/SW Cosimulation Using Virtual Synchronization Technique Speaker: Dohyung Kim, - Seoul National Univ. Authors:Dohyung Kim, Youngmin Yi, , Soonhoi Ha- Seoul National Univ., Seoul, South Korea ********************************************************************************** Session: 21 | Title: Special Session: The Titanic: What Went Wrong Day: Wednesday June 15 2005 Time: 10:30 to 12:00 | RM : 207ABC Chair: Andrew B. Kahng - Univ. of California at San Diego, La Jolla, CA Organizers: Sani Nassif Four speakers will each give a 15-minute lament of their "problems," after which moderated and timed feedback from the audience and other speakers will give 1-minute solutions and other feedback. The session will contain focused talks on a Technology problem, a Power problem, a Reliability problem, and a Methodology problem. At the end, a prize will be given for the solution that the audience votes highest in value. 21.1 The Titanic: What Went Wrong in Technology Speaker: Paul Zuchowski, - IBM Corp. Authors:Paul Zuchowski - IBM Corp., Essex Junction, VT 21.2 The Titanic: What Went Wrong in Methodology Speaker: Ward A. Vercruysse, - Advanced Micro Devices, Inc. Authors:Ward A. Vercruysse - Advanced Micro Devices, Inc., Sunnyvale, CA 21.3 The Titanic: What Went Wrong in Reliability Speaker: Claude Moughanni, - Freescale Semiconductor, Inc. Authors:Claude Moughanni - Freescale Semiconductor, Inc., Austin, TX 21.4 Bridging the Power Reduction and Estimation Gap in the Cell Processor Design Methodology Speaker: Stephen D. Posluszny, - IBM Corp. Authors:Stephen D. Posluszny - IBM Corp., Round Rock, TX ********************************************************************************** Session: 22 | Title: PANEL: Wireless Platforms: GOPS for Cents and MilliWatts Day: Wednesday June 15 2005 Time: 10:30 to 12:00 | RM : 210CD Chair: Jan Rabaey - Univ. of California, Berkeley, CA Organizers: Francine Bacchini Data communication has overtaken voice as the main force behind the growth in wireless. Opportunities offered by truly ubiquitous connectivity are tremendous, and are leading to revolutionary changes in the way computer, communication, and consumer systems operate and interact. Panelists will debate the various wireless implementation platforms that are breaking new ground, examining issues of efficiency, flexibility, and programming models. 22.1 PANEL: Wireless Platforms: GOPS for Cents and MilliWatts Speaker: Rudy Lauwereins, - IMECFrank Lane, - Flarion Technologies, Inc.Allan Cox, - 3Plus1 Technology, Inc.Ulrich Ramacher, - Infineon TechnologiesDavid Witt, - Texas Instruments, Inc. Authors: ********************************************************************************** Session: 23 | Title: Design Methods for Manufacturability Enhancements Day: Wednesday June 15 2005 Time: 10:30 to 12:00 | RM : 210AB Chair: Nagib Z. Hakim - Intel Corp., Santa Clara, CA Organizers: David Blaauw, Michael Orshansky As we sink further below the 100 nm barrier, more second order effects are entering the design/manufacturing interface. Optical Proximity Correction, Focus Variations, and other Resolution Enhancement Techniques conspire to lengthen the design and verification processes. The papers in this session attack this area from two distinct directions: from the design side using regularity - or from the CAD side developing algorithms that are aware of these effects. 23.1 Design Methodology for IC Manufacturability Based on Regular Logic-Bricks Speaker: Veerbhan Kheterpal, - Carnegie Mellon Univ. Authors:Veerbhan Kheterpal, Vyacheslav V. Rovner, Thiago G. Hersan, Dipti Motiani, Yoichi TakegawaAndrzej J. Strojwas, , Lawrence T. Pileggi, - Carnegie Mellon Univ., Pittsburgh, PA 23.2 Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions Speaker: Jie Yang, - Univ. of Michigan Authors:Jie Yang - Univ. of Michigan, Ann Arbor, MI, , Luigi Capodieci- Advanced Micro Devices, Inc., Sunnyvale, CA, , Dennis M. Sylvester- Univ. of Michigan, Ann Arbor, MI 23.3s Self-compensating Design for Focus Variation Speaker: Youngmin Kim, - Univ. of Michigan Authors:Puneet Gupta - Blaze DFM Inc., Sunnyvale, CA, , Andrew B. Kahng- Blaze DFM Inc. & Univ. of California at San Diego, La Jolla, CA, Youngmin Kim, , Dennis M. Sylvester, - Univ. of Michigan, Ann Arbor, MI 23.4s RADAR: RET-Aware Detailed Routing Using Fast Lithography Simulations Speaker: Joydeep Mitra, - Univ. of Texas Authors:Joydeep Mitra, Peng Yu, , David Z. Pan- Univ. of Texas, Austin, TX ********************************************************************************** Session: 24 | Title: Methods and Representations for Logic Synthesis Day: Wednesday June 15 2005 Time: 10:30 to 12:00 | RM : 209AB Chair: Iris Bahar - Brown Univ., Providence, RI Organizers: James Hoe, Marek Perkowski This session presents three papers addressing classical logic synthesis issues. The first paper introduces a new representation for multiple-output, incompletely specified functions. The representation, called binary-decision diagrams for characteristic functions (BDD_for_CF), is applied to efficiently decompose a function to lookup-table cascades. The second paper proposes an efficient and compact canonical form for Boolean matching under permutation and complementation of variables. The third paper investigates the design space of branch-and-bound algorithms. The paper results in two efficient algorithms for unate and binate covering and applies them to find exact solutions to three previously unsolved ESPRESSO benchmarks. 24.1 BDD Representation for Incompletely Specified Multiple-Output Logic Functions and Its Applications to Functional Decomposition Speaker: Tsutomu Sasao, - Kyushu Institute of Tech. Authors:Tsutomu Sasao, , Munehiro Matsuura- Kyushu Institute of Tech., Iizuka, Japan 24.2 A New Canonical Form for Fast Boolean Matching in Logic Synthesis and Verification Speaker: Afshin Abdollahi, - Univ. of Southern California Authors:Afshin Abdollahi, , Massoud Pedram- Univ. of Southern California, Los Angeles, CA 24.3 Effective Bounding Techniques For Solving Unate and Binate Covering Problems Speaker: Xiao Yu Li, - North Carolina State Univ. Authors:Xiao Yu Li, Matthias F. Stallmann, , Franc Brglez- North Carolina State Univ., Raleigh, NC ********************************************************************************** Session: 25 | Title: Generating Efficient Models for Analog Circuits Day: Wednesday June 15 2005 Time: 10:30 to 12:00 | RM : 208AB Chair: Richard Shi - Univ. of Washington, Seattle, WA Organizers: Koen Lampaert, Sandeep Shukla This session describes various techniques for generating efficient models for analog circuits. The first paper uses a novel operator-based model-order reduction algorithm to reduce a large linear periodically time-varying system into a smaller one. The second paper analyzes input and clock jitter effects in track and hold circuits. The last paper presents a scalable trajectory-based modeling methodology for generating on-demand macromodels for analog circuits. 25.1 Operator-based Model-Order Reduction of Linear Periodically Time-Varying Systems Speaker: Yayun Wan, - Univ. of Minnesota Authors:Yayun Wan, , Jaijeet Roychowdhury- Univ. of Minnesota, Minneapolis, MN 25.2 Simulation of the Effects of Timing Jitter in Track-and-Hold and Sample-and-Hold Circuits Speaker: Vinita Vasudevan, - Indian Institute of Tech. Authors:Vinita Vasudevan - Indian Institute of Tech., Madras, Chennai, India 25.3 Scalable Trajectory Methods for On-Demand Analog Macromodel Extraction Speaker: Saurabh K. Tiwary, - Carnegie Mellon Univ. Authors:Saurabh K. Tiwary, , Rob A. Rutenbar- Carnegie Mellon Univ., Pittsburgh, PA ********************************************************************************** Session: 26 | Title: Special Session: Emerging Directions in Wireless Day: Wednesday June 15 2005 Time: 2:00 to 4:00 | RM : 207ABC Chair: Anantha Chandrakasan - Massachusetts Institute of Technology, Cambridge, MA Organizers: Anantha Chandrakasan, Jan Rabaey This session features prominent speakers, who will identify major new trends and technologies in wireless, as well as the impacts these will have on implementation strategies, architectures, and methodologies. 26.1 Cognitive Radio Techniques for Wide Area Networks Speaker: Bill Krenik, - Texas Instruments Inc. Authors:Bill Krenik - Texas Instruments Inc., Dallas, TX 26.2 MIMO Technology for Advanced Wireless Local Area Networks Speaker: Jeffery M. Gilbert, - Atheros Communications, Inc. Authors:Jeffery M. Gilbert - Atheros Communications, Inc., Sunnyvale, CA 26.3 Challenges of Ultra Low Power Wireless System Design Speaker: Ahmad Bahai, - National Semiconductor Corp. Authors:Ahmad Bahai - National Semiconductor Corp., Santa Clara, CA 26.4 RF-MEMS in Wireless Architectures Speaker: Clark T.-C. Nguyen, - DARPA Authors:Clark T.-C. Nguyen - DARPA, Arlington, VA ********************************************************************************** Session: 27 | Title: CAD for FPGAs Day: Wednesday June 15 2005 Time: 2:00 to 4:00 | RM : 210CD Chair: Steve Trimberger - Xilinx, San Jose, CA Organizers: Patrick Lysaght, Steven Teig FPGAs are rapidly rising in importance and pose a unique set of CAD challenges. This session presents a diverse collection of new techniques from both academic and industrial researchers. 27.1 Multiplexer Restructuring for FPGA Implementation Cost Reduction Speaker: Paul Metzgen, - Altera Corp. Authors:Paul Metzgen, , Dominic Nancekievill- Altera Corp., San Jose, CA 27.2 FPGA Technology Mapping: A Study of Optimality Speaker: Andrew C. Ling, - Univ. of Toronto Authors:Andrew C. Ling - Univ. of Toronto, Toronto, Canada, Deshanand P. Singh, , Stephen D. Brown- Altera Corp., Toronto, Canada 27.3 Incremental Retiming for FPGA Physical Synthesis Speaker: Deshanand P. Singh, - Altera Corp. Authors:Deshanand P. Singh, Valavan Manohararajah, , Stephen D. Brown- Altera Corp., Toronto, Canada 27.4 Architecture-Adaptive Range Limit Windowing for Simulated Annealing FPGA Placement Speaker: Ken Eguro, - Univ. of Washington Authors:Ken Eguro, Akshay Sharma, , Scott Hauck- Univ. of Washington, Seattle, WA ********************************************************************************** Session: 28 | Title: Effective Formal Verification Using Word-level Reasoning, Bit-level Generality, and Parallelism Day: Wednesday June 15 2005 Time: 2:00 to 4:00 | RM : 210AB Chair: Howard Wong-Toi - Jasper Design Automation, Mountain View, CA Organizers: Adnan Aziz, Pei-Hsin Ho The papers in this session address the challenges of formally verifying real-world designs. The first two papers exploit designer intent inferred from the RT-level description. The third paper uses bit-level arithmetic to reduce the complexity of SAT-based BMC. The fourth paper presents a new low-cost approach to sequential redundancy removal. The final paper leverages parallelism to speed-up BDD-based reachability analysis. 28.1 Word Level Predicate Abstraction and Refinement for Verifying RTL Verilog Speaker: Himanshu Jain, - Carnegie Mellon Univ. Authors:Himanshu Jain - Carnegie Mellon Univ., Pittsburgh, PA, , Daniel Kroening- ETH Zurich, Zuerich, Switzerland, Natasha Sharygina, , Edmund M. Clarke, - Carnegie Mellon Univ., Pittsburgh, PA 28.2 Structural Search for RTL with Predicate Learning Speaker: Ganapathy Parthasarathy, - Univ. of California Authors:Ganapathy Parthasarathy, Madhu K Iyer, Kwang-Ting Cheng, , Forrest Brewer, - Univ. of California, Santa Barbara, CA 28.3 Normalization at the Arithmetic Bit Level Speaker: Markus Wedler, - Univ. of Kaiserslautern Authors:Markus Wedler, Dominik Stoffel, , Wolfgang Kunz- Univ. of Kaiserslautern, Kaiserslautern, Germany 28.4s Exploiting Suspected Redundancy Without Proving It Speaker: Hari Mony, - IBM Corp. Authors:Hari Mony, Jason R. Baumgartner, Viresh Paruthi, , Robert L. Kanzelman, - IBM Corp., Rochester, NY 28.5s Multi-threaded Reachability Speaker: Debashis Sahoo, - Stanford Univ. Authors:Debashis Sahoo - Stanford Univ., Stanford, CA, , Jawahar Jain- Fujitsu Labs. Ltd., Sunnyvale, CA, , Subramanian K. Iyer- Univ. of Texas, Austin, TX, David L. Dill, - Stanford Univ., Stanford, CA, , Allen E. Emerson, - Univ. of Texas, Austin, TX ********************************************************************************** Session: 29 | Title: Advances in Synthesis Day: Wednesday June 15 2005 Time: 2:00 to 4:00 | RM : 209AB Chair: David S. Kung - IBM Corp., Yorktown Heights, NY Organizers: Leon Stok, Soha Hassoun Reusable DFT IP modules can be created using a parameterized soft core generator. Integrated race condition and clock skew scheduling is performed using an efficient method. Leakage power and noise are increasingly important issues that must be addressed by logic synthesis. A unifying framework for modeling asynchronous pipelines allows systematic exploration of the design space. 29.1s Automatic Generation of Customized Discrete Fourier Transform IPs Speaker: James C. Hoe, - Carnegie Mellon Univ. Authors:Grace Nordin, Peter Milder, James C. Hoe, , Markus Pueschel, - Carnegie Mellon Univ., Pittsburgh, PA 29.2s Race-Condition-Aware Clock Skew Scheduling Speaker: Shih-Hsu Huang, - Chung Yuan Christian Univ. Authors:Shih-Hsu Huang, Yow-Tyng Nieh, , Feng-Pin Lu- Chung Yuan Christian Univ., Chung Li, Taiwan 29.3 Dynamic Supply Gating for Switching and Active Leakage Power Reduction Speaker: Swarup Bhunia, - Purdue Univ. Authors:Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hamid Mahmoodi, , Kaushik Roy, - Purdue Univ., West Lafayette, IN 29.4 Designing Logic Circuits for Probabilistic Computation in the Presence of Noise Speaker: Kundan Nepal, - Brown Univ. Authors:Kundan Nepal, Iris Bahar, Joseph Mundy, William R. Patterson, , Alexander Zaslavsky, - Brown Univ., Providence, RI 29.5 A Lattice-Based Framework for the Classification and Design of Asynchronous Pipelines Speaker: Peggy B. McGee, - Columbia Univ. Authors:Peggy B. McGee, , Steven M. Nowick- Columbia Univ., New York, NY ********************************************************************************** Session: 30 | Title: Coping with Buffering Day: Wednesday June 15 2005 Time: 2:00 to 4:00 | RM : 208AB Chair: Dinesh Gaitonde - Synopsys, Inc., Mountain View, CA Organizers: Dirk Stroobandt, Igor Markov This session introduces novel methods for economical buffer insertion. The first paper presents dual-Vdd buffer tree construction for power minimization under delay constraints. The next two papers focus on minimizing the overall number of repeaters in a circuit. The fourth paper resolves overlaps between repeaters and pre-existing cells. 30.1 Power Optimal Dual-Vdd Buffered Tree Considering Buffer Stations and Blockages Speaker: King Ho Tam, - Univ. of California Authors:King Ho Tam, , Lei He- Univ. of California, Los Angeles, CA 30.2 Net Weighting to Reduce Repeater Counts During Placement Speaker: Brent Goplen, - Univ. of Minnesota Authors:Brent Goplen - Univ. of Minnesota, Minneapolis, MN, , Prashant Saxena- Synopsys, Inc., Hillsboro, OR, , Sachin S. Sapatnekar- Univ. of Minnesota, Minneapolis, MN 30.3 Path Based Buffer Insertion Speaker: Cliff C.N. Sze, - Texas A&M Univ. Authors:Cliff C.N. Sze - Texas A&M Univ., College Station, TX, , Charles J. Alpert- IBM Corp., Austin, TX, Jiang Hu, , Weiping Shi, - Texas A&M Univ., College Station, TX 30.4 Diffusion-Based Placement Migration Speaker: Haoxing Ren, - IBM Corp. & Univ. of Texas Authors:Haoxing Ren, , David Z. Pan- Univ. of Texas, Austin, TX, Charles J. Alpert, , Paul Villarrubia, - IBM Corp., Austin, TX ********************************************************************************** Session: 31 | Title: PANEL: Is Methodology the Highway Out of Verification Hell? Day: Wednesday June 15 2005 Time: 4:30 to 6:30 | RM : 207ABC Chair: Gabe Moretti - Consultant, Venice, FL Organizers: Francine Bacchini Few would disagree that verification takes the lion's share of today's project resources. Given verification's tremendous burden and its painful impact on fundamental design quality and time-to-market demands, what is our industry doing in response? This panel explores where the methodology highway is taking us--is the destination heaven or just another level of Dante's inferno? 31.1 PANEL: Is Methodology the Highway Out of Verification Hell? Speaker: Harry Foster, - Jasper Design AutomationJanick Bergeron, - Synopsys, Inc.Masayuki Nakamura, - Sony Corp.Shrenik Mehta, - Sun MicrosystemsLaurent Ducousso, - STMicroelectronics Authors: ********************************************************************************** Session: 32 | Title: Impact of Process Variations on Power Day: Wednesday June 15 2005 Time: 4:30 to 6:30 | RM : 210CD Chair: Sunil Khatri - Texas A&M Univ., College Station, TX Organizers: Naehyuck Chang In this session, there are four papers that examine the impact of process variations on power. The first paper computes the full chip leakage power under process variations considering intra-die, inter-die variations and spatial correlations. The second paper examines a design of a low-power parallel system based on voltage scaling considering within-die variations and temperature fluctuations. The correlation between delay and power is the subject of the third paper. Finally, the fourth paper presents a convex optimization procedure to find the exact minimum leakage considering process variations. 32.1 Full-Chip Analysis of Leakage Power Under Process Variations, Including Spatial Correlations Speaker: Hongliang Chang, - Univ. of Minnesota Authors:Hongliang Chang, , Sachin S. Sapatnekar- Univ. of Minnesota, Minneapolis, MN 32.2 Variations-Aware Low-Power Design with Voltage Scaling Speaker: Navid Azizi, - Univ. of Toronto Authors:Navid Azizi - Univ. of Toronto, Toronto, Canada, Muhammad M. Khellah, , Vivek De- Intel Corp., Hillsboro, OR, Farid N. Najm, - Univ. of Toronto, Toronto, Canada 32.3 Accurate and Efficient Parametric Yield Estimation Considering Correlated Variations in Leakage Power and Performance Speaker: Ashish Srivastava, - Univ. of Michigan Authors:Ashish Srivastava, Saumil S. Shah, Kanak B. Agarwal, Dennis M. Sylvester, David Blaauw, Stephen Director, - Univ. of Michigan, Ann Arbor, MI 32.4 Leakage Minimization of Nano-scale Circuits in the Presence of Systematic and Random Variations Speaker: Sarvesh Bhardwaj, - Arizona State Univ. Authors:Sarvesh Bhardwaj, , Sarma B. Vrudhula- Arizona State Univ., Tempe, AZ ********************************************************************************** Session: 33 | Title: Special Session: The Best of Wireless at ISSCC Day: Wednesday June 15 2005 Time: 4:30 to 6:30 | RM : 210AB Chair: Wanda Gass - Texas Instruments, Inc., Dallas, TX Organizers: Wanda Gass This is the now-traditional Best of ISSCC session at DAC. This year, we selected the best of wireless-related papers at ISSCC to fit into the theme of Wireless Day. 33.1 A 135Mb/s DVB-S2 Compliant CODEC Based on 64,800b LDPC and BCH Codes (ISSCC Paper 24.3) Speaker: Pascal Urard, - STMicroelectronics Authors:Pascal Urard, E. Yeo, L. Paumier, P. Georgelin, T. MichelV. Lebars, , E. Lantreibecq, - STMicroelectronics, Crolles, France, , B. Gupta, - W5Networks, Inc., Palo Alto, CA 33.2 A 180Ms/s 162Mb/s Wideband Three-Channel Baseband and MAC Processor for 802.11a/b/g (ISSCC Paper 24.7) Speaker: Manish Bhardwaj, - Engim, Inc. Authors:Manish Bhardwaj, , C. Briggs- Engim, Inc., Acton, MA, , A. Chandrakasan- Massachusetts Institute of Tech., Cambridge, MAC. Eldridge, J. GoodmanT. Nightingale, S. Sharma, G. Shin, D. Shoemaker, A. Sinha R. Venkatesan J. Winston W. Zhou 33.3 90 nm Low Leakage SoC Design Techniques for Wireless Applications Speaker: Michael Wagner, - Texas Instruments, Inc. Authors:Philippe Royannez, , H. Mair- Texas Instruments, Villeneuve Loubet, France, F. Dahan, M. Wagner, M. StreeterL. Boutel, J. Blasquez, H. Clasen, G. Semino, J. Dong 33.4 A 24GHz Phased-Array Transmitter in 0.18µm CMOS (ISSCC 11.7) Speaker: Ali Hajimiri, - California Institute of Tech. Authors:Ali Hajimiri, Arun Natarajan, , Abbas Komijani- California Institute of Tech., Pasadena, CA ********************************************************************************** Session: 34 | Title: Architectural Support for Communication Day: Wednesday June 15 2005 Time: 4:30 to 6:30 | RM : 209AB Chair: Petru Eles - Linkoping University, Linkoping, Sweden Organizers: Marcello Coppola, Peter Marwedel Communication is quickly becoming one of the most important problems in high-performance and system-on-chip designs. The first two papers present hardware to reduce snooping in MPSoC and adaptivity support. The third paper is on floorplan aware synthesis of communication architectures. Finally, the last two propose architectures for dynamic topology and traffic shaping. 34.1 Cache Coherence Support for Non-shared Bus Architecture on Heterogeneous MPSoCs Speaker: Taeweon Suh, - Georgia Institute of Tech. Authors:Taeweon Suh, , Hsien-Hsin S. Lee- Georgia Institute of Tech., Atlanta, GA, , Daehyun Kim- Intel Corp., Santa Clara, CA 34.2 A Low-Latency Router Supporting Adaptivity for On-Chip Interconnects Speaker: N. Vijaykrishnan, - Pennsylvania State Univ. Authors:Jongman Kim, Dongkook Park, Theocharis G. Theocharides, N. Vijaykrishnan, , Chita R. Das, - Pennsylvania State Univ., University Park, PA 34.3 Floorplan-aware Automated Synthesis of Bus-based Communication Architectures Speaker: Sudeep Pasricha, - Univ. of California Authors:Sudeep Pasricha, Nikil Dutt, , Elaheh Bozorgzadeh- Univ. of California, Irvine, CA, Mohamed Ben-Romdhane, - Conexant Systems Inc., Newport Beach, CA 34.4s FLEXBUS: A High-Performance System-on-Chip Communication Architecture with a Dynamically Configurable Topology Speaker: Krishna Sekar, - Univ. of California at San Diego Authors:Krishna Sekar - Univ. of California at San Diego, La Jolla, CA, Kanishka Lahiri, , Anand Raghunathan- NEC-Labs America, Inc., Princeton, NJ, Sujit Dey, - Univ. of California at San Diego, La Jolla, CA 34.5s Traffic Shaping for an FPGA based SDRAM Controller with Complex QoS Requirements Speaker: Sven Heithecker, - Technical Univ. of Braunschweig Authors:Sven Heithecker, , Rolf Ernst- Technical Univ. of Braunschweig, Braunschweig, Germany ********************************************************************************** Session: 35 | Title: New Approaches to Physical Design Problems Day: Wednesday June 15 2005 Time: 4:30 to 6:30 | RM : 208AB Chair: Chung-Kuan Cheng - Univ. of California at San Diego, La Jolla, CA Organizers: Louis Scheffer, Malgorzata Marek-Sadowska Traditional physical design problems are attacked by new methods and algorithms. This includes a floorplanner that considers micro-architecture, two new core placement algorithms, and an implementation of the recent X routing ideas. 35.1 Microarchitecture-Aware Floorplanning Using a Statistical Design of Experiments Approach Speaker: Vidyasagar Nookala, - Univ. of Minnesota Authors:Vidyasagar Nookala, Ying Chen, David Lilja, , Sachin S. Sapatnekar, - Univ. of Minnesota, Minneapolis, MN 35.2 Timing-Driven Placement by Grid-Warping Speaker: Zhong Xiu, - Carnegie Mellon Univ. Authors:Zhong Xiu, , Rob A. Rutenbar- Carnegie Mellon Univ., Pittsburgh, PA 35.3 Faster and Better Global Placement by a New Transportation Algorithm Speaker: Ulrich Brenner, - Universität Bonn Authors:Ulrich Brenner, , Markus Struzyna- Universität Bonn, Bonn, Germany 35.4 Multilevel Full-Chip Routing for the X-Based Architecture Speaker: Tsung-Yi Ho, - National Taiwan Univ. Authors:Tsung-Yi Ho, Chen-Feng Chang, Yao-Wen Chang, , Sao-Jie Chen, - National Taiwan Univ., Taipei, Taiwan ********************************************************************************** Session: 36 | Title: Special Session: MATLAB ® - The Other Emerging System-Design Language Day: Thursday June 16 2005 Time: 8:30 to 10:00 | RM : 207ABC Chair: Randy Allen - Catalytic, Inc., Palo Alto, CA Organizers: Steven Tjiang This special session addresses the requirements to make MATLAB® suitable for real implementation. It will demonstrate design and verification flows starting with MATLAB for DSPs, FPGAs and ASICs. 36.1 MATLAB as a Design Environment for Wireless ASIC Design Speaker: Erik Lindskog, - Beceem Communications, Inc. Authors:Erik Lindskog - Beeceem Communications, Inc., Santa Clara, CA 36.2 MATLAB Extensions for the Development, Testing, and Verification of Real-Time DSP Program Development Speaker: David P. Magee, - Texas Instruments, Inc. Authors:David P. Magee - Texas Instruments, Inc., Dallas, TX 36.3 MATLAB as a Development Environment for FPGA Design Speaker: Tejas Bhatt, - Nokia Americas Authors:Tejas Bhatt, , Dennis McCain- Nokia Americas, Irving, TX ********************************************************************************** Session: 37 | Title: PANEL: Should Our Power Approach Be Current? Day: Thursday June 16 2005 Time: 8:30 to 10:00 | RM : 210CD Chair: Tim Fox - Deutsche Bank, Baltimore, MD Organizers: Lou Covey, Susan Lippincott Mack The metric for success has changed from performance and area to power consumption in nanometer SoC designs, especially in the huge market for handheld/wireless consumer electronics. Although "power" is often the stated concern, current is the real issue. Leaders from across the silicon design chain discuss how they cope with leakage current today and their vision to address the problem in order for the electronics industry to successfully move below 90 nm. 37.1 PANEL: Should Our Power Approach be Current? Speaker: David Heacock, - Texas Instruments, Inc.Vess Johnson, - Nascentric, Inc.Andrew Yang, - Apache Design Solutions, Inc.Ed Huijbregts, - Magma Design Automation, Inc.Paul Zuchowski, - IBM Corp. Authors: ********************************************************************************** Session: 38 | Title: Emerging Ideas in Energy Management Techniques Day: Thursday June 16 2005 Time: 8:30 to 10:00 | RM : 210AB Chair: Rajesh Gupta - Univ. of California at San Diego, San Diego, CA Organizers: Diana Marculescu, Taewhan Kim This collection of papers explores some of the new ideas for energy management in a wide variety of scenarios. 38.1 DTM: Dynamic Tone Mapping for Backlight Scaling Speaker: Ali Iranli, - Univ. of Southern California Authors:Ali Iranli, , Massoud Pedram- Univ. of Southern California, Los Angeles, CA 38.2 Application/Architecture Power Co-Optimization for Embedded Systems Powered by Renewable Sources Speaker: Dexin Li, - Univ. of California Authors:Dexin Li, , Pai H. Chou- Univ. of California, Irvine, CA 38.3s User-Perceived Latency Driven Voltage Scaling for Interactive Applications Speaker: Le Yan, - Princeton Univ. Authors:Le Yan, Lin Zhong, , Niraj K. Jha- Princeton Univ., Princeton, NJ 38.4s System-Level Energy-Efficient Dynamic Task Scheduling Speaker: Chaitali Chakrabarti, - Arizona State Univ. Authors:Jianli Zhuo, , Chaitali Chakrabarti- Arizona State Univ., Tempe, AZ ********************************************************************************** Session: 39 | Title: Advances in Optimization of Mixed-signal Circuits Day: Thursday June 16 2005 Time: 8:30 to 10:00 | RM : 209AB Chair: Koen Lampaert - Mindspeed Technologies, Inc., Newport Beach, CA Organizers: Geert Van Der Plas, Sandeep Shukla This session reports recent advances in optimization of mixed-signal circuits. The session starts with a paper on optimization with ellipsoidal uncertainty for robust analog circuit design. In the second paper, a unified framework for the optimization of FIR equalization filters is presented. In the third paper, template-driven layout optimization with inclusion of parasitics is presented. In the last paper, an approach for inductor synthesis is presented that includes global and local optimization. 39.1 OPERA: OPtimization with Ellipsoidal Uncertainty for Robust Analog IC design Speaker: Yang Xu, - Carnegie Mellon Univ. Authors:Yang Xu - Carnegie Mellon Univ., Pittsburgh, PA, , Kan-Lin Hsiung- Stanford Univ., Stanford, CA, , Xin Li- Carnegie Mellon Univ., Pittsburgh, PA, Ivan Nausieda, - Harvard Univ., Cambridge, MA, , Stephen Boyd, - Stanford Univ., Stanford, CA, , Larry T. Pileggi, - Carnegie Mellon Univ., Pittsburgh, PA 39.2 A Unified Optimization Framework for Equalization Filter Synthesis Speaker: Jihong Ren, - Univ. of British Columbia Authors:Jihong Ren, , Mark R. Greenstreet- Univ. of British Columbia, Vancouver, BC, Canada 39.3s Parasitic-Aware Template-Driven Optimization of Analog Integrated Circuit Layouts Speaker: Sambuddha Bhattacharya, - Univ. of Washington Authors:Sambuddha Bhattacharya, Nuttorn Jangkrajarng, , J. Richard Shi- Univ. of Washington, Seattle, WA 39.4s Multi-Level Approach for Integrated Spiral Inductor Optimization Speaker: Arthur Nieuwoudt, - Rice Univ. Authors:Arthur Nieuwoudt, , Yehia Massoud- Rice Univ., Houston, TX ********************************************************************************** Session: 40 | Title: Circuit Performance Under Parameter Variation Day: Thursday June 16 2005 Time: 8:30 to 10:00 | RM : 208AB Chair: L. Miguel Silveira - INESC-ID/IST/Cadence Labs, Lisbon, Portugal Organizers: Charlie Chung-Ping Chen, Joel Phillips This session contains a variety of contributions motivated by circuit analysis under process variation. The first paper argues that in practical applications, adequate statistical analysis of timing can be performed with relatively simple path-based methods. The second paper surveys variability modeling for circuit applications. The final paper discusses sensitivity analysis in the context of power grid modeling. 40.1 Statistical Static Timing Analysis: How Simple Can We Get? Speaker: Chirayu S. Amin, - Northwestern Univ. Authors:Chirayu S. Amin - Northwestern Univ., Evanston, IL, Noel Menezes, Kip Killpack, , Florentin Dartu, - Intel Corp., Hillsboro, OR, , Yehea Ismail, - Northwestern Univ., Evanston, IL, Umakanta Choudhury, , Nagib Hakim, - Intel Corp., Hillsboro, OR 40.2 Mapping Statistical Process Variations Toward Circuit Performance Variability: An Analytical Modeling Approach Speaker: Yu Cao, - Arizona State Univ. Authors:Yu Cao, , Lawrence T. Clark- Arizona State Univ., Tempe, AZ 40.3 Power Grid Simulation Via Efficient Sampling-Based Sensitivity Analysis and Hierarchical Symbolic Relaxation Speaker: Peng Li, - Texas A&M Univ. Authors:Peng Li - Texas A&M Univ., College Station, TX ********************************************************************************** Session: 41 | Title: Special Session: Formally Verifying Your 10-Million Gate Design Day: Thursday June 16 2005 Time: 10:30 to 12:00 | RM : 207ABC Chair: Robert Damiano - Synopsys, Inc., Hillsboro, OR Organizers: Pei-Hsin Ho In this special session verification practitioners from IBM, nVIDIA and STMicroelectronics share their best known methods and success stories of employing formal property verification to achieve better design quality and shorter design cycle. 41.1 Formal Verification: IsIt Real Enough? Speaker: Yaron Wolfsthal, - IBM Corp. Authors:Yaron Wolfsthal, , Rebecca M. Gott- IBM Corp., Poughkeepsi, NY 41.2 Can We Really Do Without the Support of Formal Methods in the Verification of Large Designs? Speaker: Umberto Rossi, - STMicroelectronics Authors:Umberto Rossi - STMicroelectronics, Milano, Italy 41.3 Streamline Verification Process with Formal Property Verification to Meet Highly Compressed Design Cycle Speaker: Prosenjit Chattterjee, - NVIDIA Corp. Authors:Prosenjit Chattterjee - NVIDIA Corp., Santa Clara, CA ********************************************************************************** Session: 42 | Title: Embedded Hardware and System Software Day: Thursday June 16 2005 Time: 10:30 to 12:15 | RM : 210CD Chair: Eugenio Villar - Universidad de Cantabria, Santander, Spain Organizers: Chi-Ying Tsui, Pai Chou This session includes four papers describing embedded system hardware and software closely linked to that hardware. The first paper proposes an architecture which is relevant for fast internet routing. It is followed by a paper presenting an approach for speech recognition that takes the limited performance of portable devices into account. The third paper comprises algorithms for low-overhead fault-tolerant execution of Java programs. The final paper addresses multiprocessor embedded systems which often have processor-local caches and a shared memory. If the system's code is available at design time, we can maximize cache hits by rearranging code in memory. 42.1 TCAM Enabled On-Chip Logic Minimization Speaker: Rabi Mahapatra, - Texas A&M Univ. Authors:Seraj Ahmad, , Rabi Mahapatra- Texas A&M Univ., College Station, TX 42.2 Hardware Speech Recognition for User Interfaces in Low Cost, Low Power Devices Speaker: Sergiu Nedevschi, - Univ. of California Authors:Sergiu Nedevschi, Rabin K. Patra, , Eric A. Brewer- Univ. of California, Berkeley, CA 42.3 Improving Java Virtual Machine Reliability for Memory-Constrained Embedded Systems Speaker: Guangyu Chen, - Pennsylvania State Univ. Authors:Guangyu Chen, , Mahmut Kandemir- Pennsylvania State Univ., University Park, PA 42.4s Frequency-Based Code Placement for Embedded Multiprocessors Speaker: Corey M. Goldfeder, - Columbia Univ. Authors:Corey M. Goldfeder - Columbia Univ., New York, NY ********************************************************************************** Session: 43 | Title: Power Estimation and Design Tradeoffs Day: Thursday June 16 2005 Time: 10:30 to 12:00 | RM : 210AB Chair: Kimiyoshi Usami - Shibaura Institute of Technology, Saitama, Japan Organizers: Jerry Frenkil This session contains papers that address low power design at several levels. The first paper describes a novel and fast power estimation using hardware emulation. The second paper explores tradeoffs in power and performance in configurable processors. Power control in a network processor using clock gating is decribed in the third paper. The fourth paper presents a technique that overcomes delay variation by bulk voltage control. 43.1 Power Emulation: A New Paradigm for Power Estimation Speaker: Joel D. Coburn, - NEC-Labs America Authors:Joel D. Coburn, Srivaths Ravi, , Anand Raghunathan- NEC-Labs America, Princeton, NJ 43.2 Implementing Low-Power Configurable Processors - Practical Options and Tradeoffs Speaker: Ashish Dixit, - Tensilica, Inc. Authors:John H. Wei, , Chris Rowen- Tensilica, Inc., Santa Clara, CA 43.3s Low Power Network Processor Design Using Clock Gating Speaker: Yan Luo, - Univ. of California Authors:Yan Luo, Jia Yu, Jun Yang, , Laxmi Bhuyan, - Univ. of California, Riverside, CA 43.4s A Variation-Tolerant Sub-Threshold Design Approach Speaker: Nikhil Jayakumar, - Texas A&M Univ. Authors:Nikhil Jayakumar, , Sunil Khatri- Texas A&M Univ., College Station, TX ********************************************************************************** Session: 44 | Title: Programmable Architectures Day: Thursday June 16 2005 Time: 10:30 to 12:00 | RM : 209AB Chair: Pedro Diniz - USC Information Sciences Institute, Marina Del Rey, CA Organizers: Ryan Kastner, Steven Teig The exploration of programmable architectures, particularly for low power, is an active area of contemporary research. This session addresses three distinct topics: power management, dynamic reconfiguration, and IP mapping. 44.1 Leakage Efficient Chip-Level Dual-Vdd Assignment with Time Slack Allocation for FPGA Power Reduction Speaker: Yan Lin, - Univ. of California Authors:Yan Lin, , Lei He- Univ. of California, Los Angeles, CA 44.2 Logic Block Clustering of Large Designs for Channel Width Constrained FPGAs Speaker: Marvin Tom, - Univ. of British Columbia Authors:Marvin Tom, , Guy Lemieux- Univ. of British Columbia, Vancouver, BC, Canada 44.3 Dynamic Reconfiguration with Binary Translation: Breaking the ILP barrier with Software Compatibility Speaker: Antonio Carlos S. Beck Filho, - UFRGS Authors:Antonio Carlos S. Beck Filho, , Luigi Carro- UFRGS, Porto Alegre, Brazil ********************************************************************************** Session: 45 | Title: SAT: Cool Algorithms and Hot Applications Day: Thursday June 16 2005 Time: 10:30 to 12:00 | RM : 208AB Chair: Carl Pixley - Synopsys, Inc., Hillsboro, OR Organizers: Harry Foster, Rajeev Ranjan Recent advances in SAT have taken formal verification capabilities to a new level. The first paper shows a novel method for extending SAT techniques for liveness properties. The next two papers describe advanced learning techniques. The last paper improves the performance of abstraction refinement for property checking. 45.1 Beyond Safety: Customized SAT-based Model Checking Speaker: Malay Ganai, - NEC-Labs America, Inc. Authors:Malay Ganai, , Aarti Gupta- NEC-Labs America, Inc., Princeton, NJ, , Pranav Ashar- Real Intent Inc., Santa Clara, CA 45.2 Efficient SAT Solving: Beyond Supercubes Speaker: Alan J. Hu, - Univ. of British Columbia Authors:Domagoj Babic, Jesse D. Bingham, , Alan J. Hu- Univ. of British Columbia, Vancouver, BC, Canada 45.3s Prime Clauses for Fast Enumeration of Satisfying Assignments to Boolean Circuits Speaker: Hoonsang Jin, - Univ. of Colorado Authors:Hoonsang Jin, , Fabio Somenzi- Univ. of Colorado, Boulder, CO 45.4s Dynamic Abstraction Using SAT-based BMC Speaker: Liang Zhang, - Cadence Design Systems, Inc. Authors:Liang Zhang - Cadence Design Systems, Inc., San Jose, CA, , Mukul R. Prasad- Fujitsu Labs Ltd., Sunnyvale, CA, , Michael S. Hsiao- Virginia Polytechnic Inst., Blacksburg, VA, Thomas Sidle, - Fujitsu Labs Ltd., Sunnyvale, CA ********************************************************************************** Session: 46 | Title: Special Session: DFM and Variability: Theory and Practice Day: Thursday June 16 2005 Time: 2:00 to 4:00 | RM : 207ABC Chair: Chandu Visweswariah - IBM Corp., Yorktown Heights, NY Organizers: Michael Orshansky, Tanay Karnik This session will present a series of short (15-minute) talks that consider multiple facets of the design for manufacturability paradigm. The topics include (1) measuring interconnect variability and its effect on parasitic extraction, (2) challenges of implementing a library-based DFM strategy and the interaction between foundry and designer, (3) new circuit design techniques for robust operation, (4) the need for statistical timing analysis, (5) CAD solution for variation-aware timing analysis and optimization, and finally (6) the economic justification of implementing a DFM flow. The talks will be followed by a 30-minute Q&A with a panel of authors. On the theory side, the key focus is circuit and CAD solutions to deal with variability, and updated assessments of the impact of BEOL variations. Commercial EDA is incrementally extending existing platforms. On the practice side, the focus is on economic justification of DFM, as well as the interaction between foundry and designer. 46.1s BEOL Variabiity and Impact on RC Extraction Speaker: Nagaraj NS, - Texas Instruments, Inc. Authors:Nagaraj NS - Texas Instruments, Inc., Dallas, TX 46.2s An Effective DFM Strategy Requires Accurate Process and IP Pre-Characterization Speaker: Carlo Guardiani, - PDF Solutions, Inc. Authors:Carlo Guardiani, Massimo Bertoletti, Christoph Dolainsky, Nicola Dragone, Marco Malcotti, Patrick McNamara, - PDF Solutions, Inc., San Jose, CA 46.3s Variation-Tolerant Circuits: Circuit Solutions and Techniques Speaker: Vivek De, - Intel Corp. Authors:Vivek De - Intel Corp., Hillsboro, OR 46.4s On the Need for Statistical Timing Analysis Speaker: Farid N. Najm, - Univ. of Toronto Authors:Farid N. Najm - Univ. of Toronto, Toronto, Canada 46.5s CAD Tools for Variation Tolerance Speaker: David Blaauw, - Univ. of Michigan Authors:David Blaauw, , Kaviraj S. Chopra- Univ. of Michigan, Ann Arbor, MI 46.6s Are There Economic Benefits in DFM? Speaker: Riko Radojcic, - QUALCOMM Incorporated Authors:Matt Nowak, , Riko Radojcic- QUALCOMM Incorporated, San Diego, CA ********************************************************************************** Session: 47 | Title: Tools and Methods for the Verification of Processors and Processor-Based Systems Day: Thursday June 16 2005 Time: 2:00 to 4:00 | RM : 210CD Chair: Raghuram Tupuri - AMD, Austin, TX Organizers: Avi Ziv, Erich Marschner Modern systems are increasingly becoming microprocessor-based. Functional verification of microprocessors has long been recognized as the toughest challenge in verification. The papers in this session stress the need for proper verification planning, highlight the need for test plan automation, and illustrate the use of sophisticated test generation techniques to thoroughly cover corner cases. Case studies highlight the application of a combination of verification techniques to successfully verify these complex systems. 47.1 A Generic Micro-Architectural Test Plan Approach for Microprocessor Verification Speaker: Eyal Bin, - IBM Corp. Authors:Allon Adir, Hezi Azatchi, Eyal Bin, Ofer Peled, , Kirill Shoikhet, - IBM Corp., Haifa, Israel 47.2s IODINE: A Tool to Automatically Infer Dynamic Invariants for Hardware Designs Speaker: Sudheendra Hangal, - Sun Microsystems Authors:Sudheendra Hangal, , Naveen Chandra- Sun Microsystems, Bangalore, India, , Sridhar Narayanan- P.A. Semi Inc., Santa Clara, CA, Sandeep Chakravorty, - Sun Microsystems, Bangalore, India 47.3s VLIW ? A Case Study of Parallelism Verification Speaker: Michal Rimon, - IBM Corp. Authors:Allon Adir, , Yaron Arbetman- IBM Corp., Haifa, Israel, Massimo A Calligaro, , Andrew Cofler, - STMicroelectronics, Grenoble Cedex, France, , Bella Dubrov, - IBM Corp., Haifa, Israel, , Gabriel Duffy, - STMicroelectronics, Grenoble Cedex, France, Yossi Lichtenstein, Michal Rimon, Michael Vinov 47.4 StressTest: An Automatic Approach to Test Generation via Activity Monitors Speaker: Ilya Wagner, - Univ. of Michigan Authors:Ilya Wagner, Valeria Bertacco, , Todd Austin- Univ. of Michigan, Ann Arbor, MI 47.5 Smart Diagnostics for Configurable Processor Verification Speaker: Sadik Ezer, - Tensilica, Inc. Authors:Sadik Ezer, , Scott Johnson- Tensilica, Inc., Santa Clara, CA ********************************************************************************** Session: 48 | Title: Electrical Optimization for Physical Synthesis Day: Thursday June 16 2005 Time: 2:00 to 4:00 | RM : 210AB Chair: Gi-Joon Nam - IBM, Austin, TX Organizers: Patrick Groeneveld, Phiroze Parakh This session deals with novel power and delay optimization techniques in placement. The first paper presents a method that that reduces power by clustering registers. The following paper performs placement using a new differential timing analysis model. The final two papers both attack the optimization through novel analytical methods. 48.1 Power Aware Placement Speaker: Qinke Wang, - Univ. of California at San Diego Authors:Yongseok Cheon, , Pei-Hsin Ho- Synopsys, Inc., Portland, OR, Andrew B. Kahng, Sherief Reda, , Qinke Wang, - Univ. of California at San Diego, La Jolla, CA 48.2 How Accurately Can We Model Timing in A Placement Engine? Speaker: Amit Chowdhary, - Intel Corp. Authors:Amit Chowdhary, Karthik Rajagopal, Satish Venkatesan, Tung Cao, , Vladimir Tiourin, - Intel Corp., Santa Clara, CA, , Yegna Parasuram, - Sierra Design Automation, Inc., Santa Clara, CA, , Bill Halpin, - Synplicity, Inc., Sunnyvale, CA 48.3 Efficient and Accurate Gate Sizing with Piecewise Convex Delay Models Speaker: Hiran K. Tennakoon, - Univ. of Washington Authors:Hiran K. Tennakoon, , Carl Sechen- Univ. of Washington, Seattle, WA 48.4 Freeze: Engineering a Fast Repeater Insertion Solver for Power Minimization Using the Ellipsoid Method Speaker: Xun Liu, - North Carolina State Univ. Authors:Yuantao Peng, , Xun Liu- North Carolina State Univ., Raleigh, NC ********************************************************************************** Session: 49 | Title: Optimization Techniques in High-Level Synthesis Day: Thursday June 16 2005 Time: 2:00 to 4:00 | RM : 209AB Chair: Matt Moe - Forte Design Systems, Pittsburgh, PA Organizers: John Sanguinetti, Stephen Edwards High Level Synthesis is fundamentally about optimizing the resulting design. The papers in this session cover a variety of optimization techniques from minimizing the bit width of data values to creating fault-tolerant biochips. Papers include a technique to minimize buffer requirements and a technique to efficiently analyze pointers in C source code. 49.1 Minimising Buffer Requirements of Synchronous Dataflow Graphs with Model-Checking Speaker: Sander Stuijk, - Eindhoven Univ. of Technology Authors:Marc Geilen, Twan Basten, , Sander Stuijk- Eindhoven Univ. of Technology, Eindhoven, Netherlands 49.2 Unified High-Level Synthesis and Module Placement for Defect-Tolerant Microfluidic Biochips Speaker: Fei Su, - Duke Univ. Authors:Fei Su, , Krishnendu Chakrabarty- Duke Univ., Durham, NC 49.3 Towards Scalable Flow and Context Sensitive Pointer Analysis Speaker: Jianwen Zhu, - Univ. of Toronto Authors:Jianwen Zhu - Univ. of Toronto, Toronto, ON, Canada 49.4s MiniBit: Bit-Width Optimization via Affine Arithmetic Speaker: Dong-U Lee, - Imperial College Authors:Dong-U Lee, Altaf Abdul Gaffar, Oskar Mencer, , Wayne Luk, - Imperial College, London, UK 49.5s A Non-Parametric Approach for Dynamic Range Estimation of Nonlinear Systems Speaker: Bin Wu, - Univ. of Toronto Authors:Bin Wu, Jianwen Zhu, , Farid N. Najm- Univ. of Toronto, Toronto, ON, Canada ********************************************************************************** Session: 50 | Title: Testing for Process- and Timing-Related Faults Day: Thursday June 16 2005 Time: 2:00 to 4:00 | RM : 208AB Chair: Nicola Nicolici - McMaster University, Hamilton, Canada Organizers: Gordon Roberts, Kazumi Hatayama This session considers the impact of process variations and defects on various test algorithms and techniques, such as path delay test compaction, digital-to-analog converter type tests, memory tests and transient fault type tests. 50.1 Path Delay Test Compaction with Process Variation Tolerance Speaker: Xiaoqing Wen, - Kyushu Institute of Tech. Authors:Seiji Kajihara, Masayasu Fukunaga, , Xiaoqing Wen- Kyushu Institute of Tech., Iizuka, JapanToshiyuki Maeda, Shuji Hamada, Yasuo Sato, - STARC, Yokohama, Japan 50.2 A DFT Approach for Diagnosis and Process Variation-Aware Structural Test of Thermometer Coded Current Steering DACs Speaker: Rasit O. Topaloglu, - Univ. of California at San Diego Authors:Rasit O. Topaloglu, , Alex Orailoglu- Univ. of California at San Diego, La Jolla, CA 50.3 Resistive-Open Defect Injection in SRAM Core-Cell: Analysis and Comparison between 0.13 µm and 90 nm Technologies Speaker: Patrick Girard, - LIRMM Authors:Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, , Arnaud Virazel, - LIRMM, Montpellier, France, , Magali Bastian Hage-Hassan, - Infineon Tech., Sophia-Antipolis, France 50.4 Asynchronous Circuits Transient Faults Sensitivity Evaluation Speaker: Yannick Monnet, - TIMA Lab. Authors:Yannick Monnet, Marc Renaudin, , Regis Leveugle- TIMA Lab., Grenoble, France ********************************************************************************** Session: 51 | Title: Special Session: Hierarchical Design and Design Space Exploration of Analog Integrated Circuits Day: Thursday June 16 2005 Time: 4:30 to 6:00 | RM : 207ABC Chair: Erich Barke - Univ. of Hannover, Hannover, Germany Organizers: Helmut Graeb This session presents the leading work in analog design space exploration which is an important prerequisite for top-down synthesis flows. The research presented is grounded in real industrial design problems and has practical application. 51.1 Deterministic Approaches to Analog Performance Space Exploration Speaker: Daniel Mueller, - Tech. Univ. of Munich Authors:Daniel Mueller, Guido Stehr, Helmut Graeb, , Ulf Schlichtmann, - Tech. Univ. of Munich, Munich, Germany 51.2 Mixed-Signal Design Space Exploration Through Analog Platforms Speaker: Fernando De Bernardinis, - Univ. of California Authors:Fernando De Bernardinis - Univ. of California, Berkeley, CA, , Pierluigi Nuzzo- Univ. of Pisa, Pisa, Italy, , Alberto Sangiovanni-Vincentelli- Univ. of California, Berkeley, CA 51.3 Performance Space Modeling for Hierarchical Synthesis of Analog Integrated Circuits Speaker: Georges Gielen, - Katholieke Universiteit Leuven Authors:Georges Gielen, Trent McConaghy, , Tom Eeckelaert- Katholieke Universiteit Leuven, Leuven, Belgium ********************************************************************************** Session: 52 | Title: PANEL: Platform ASIC Apprentices: Who Will Survive Your Boardroom? Day: Thursday June 16 2005 Time: 4:30 to 6:00 | RM : 210CD Chair: Ron Wilson - EE Times, San Mateo, CA Organizers: Joe Gianelli Moore’s law delivers higher performance and lower cost for FPGAs and ASICs alike, but at the 90 nm process node and below, design schedules using the traditional cell-based ASIC design methodology hit a wall of uncertainty. At 90 nm and below an emerging alternative, or apprentice, ASIC design platform is either Platform ASIC or FPGAs. Which alternative will survive your board room? 52.1 PANEL: Platform ASIC Apprentices: Who Will Survive Your Board Room? Speaker: Christopher L. Hamlin, - LSI Logic Corp.Ivo Bolsens, - Xilinx, Inc.Richard Tobias, - Toshiba Corp.Ken McElvain, - Synplicity, Inc.Raul Camposano, - Synopsys, Inc. Authors: ********************************************************************************** Session: 53 | Title: Dynamic Voltage Scaling Day: Thursday June 16 2005 Time: 4:30 to 6:00 | RM : 210AB Chair: Massoud Pedram - Univ. of Southern California, Los Angeles, CA Organizers: Diana Marculescu, Trevor Mudge Dynamic Voltage Scaling has become one of the most popular topics for research. This session brings together some of the best recent work in the area. 53.1 Quasi-Static Assignment of Voltages and Optional Cycles for Maximizing Rewards in Real-Time Systems with Energy Constraints Speaker: Luis A. Cortes, - Volvo Truck Corp. & Linkoping Univ. Authors:Luis A. Cortes, Petru Eles, , Zebo Peng- Linkoping Univ., Linköping, Sweden 53.2 DC-DC Converter-Aware Power Management for Battery-Operated Embedded Systems Speaker: Yongseok Choi, - Seoul National Univ. Authors:Yongseok Choi, Naehyuck Chang, , Taewhan Kim- Seoul National Univ., Seoul, Republic of Korea 53.3s Energy Optimal Speed Control of Devices with Discrete Speed Sets Speaker: Ravishankar Rao, - Arizona State Univ. Authors:Ravishankar Rao, , Sarma Vrudhula- Arizona State Univ., Tempe, AZ 53.4s Optimal Procrastinating Voltage Scheduling for Hard Real-Time Systems Speaker: Yan Zhang, - Univ. of Virginia Authors:Yan Zhang, Zhijian Lu, Mircea R. Stan, John C. Lach, , Kevin Skadron, - Univ. of Virginia, Charlottesville, VA ********************************************************************************** Session: 54 | Title: New Directions in FPGA Technologies Day: Thursday June 16 2005 Time: 4:30 to 6:00 | RM : 209AB Chair: Andre DeHon - California Institute of Technology, Pasadena, CA Organizers: Jens Palsberg, Ryan Kastner Scaling trends require new ideas to keep up with the relentless pace of Moore's Law. This session presents both new device technologies and innovations for existing fabrics. 54.1 Flexible ASIC: Shared Masking for Multiple Media Processors Speaker: Jennifer L. Wong, - Univ. of California Authors:Jennifer L. Wong, Farinaz Koushanfar, , Miodrag Potkonjak- Univ. of California, Los Angeles, CA 54.2 Device and Architecture Co-Optimization for FPGA Power Reduction Speaker: Lerong Cheng, - Univ. of California Authors:Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, , Lei He, - Univ. of California, Los Angeles, CA 54.3 Exploring Technology Alternatives for Nano-Scale FPGA Interconnects Speaker: Aman Gayasen, - Pennsylvania State Univ. Authors:Aman Gayasen, Vijaykrishnan Narayanan, , Mary Jane Irwin- Pennsylvania State Univ., University Park, PA ********************************************************************************** Session: 55 | Title: Reduced-Order Modeling Day: Thursday June 16 2005 Time: 4:30 to 6:00 | RM : 208AB Chair: Janet Wang Roveda - Univ. of Arizona, Tucson, AZ Organizers: Byron Krauter, Vikram Jandhyala This session overviews the latest developments in reduced order modeling. The first paper presents a fast technique for analyzing the time-domain response of interconnects, using an elegantly simple method based on piecewise linear waveform models. The second paper uses convex optimization techniques for model-order reduction, using an approach similar to rational approximation. Next, a procedure that incorporates the skin effect to build an Arnoldi-based passivity preserving model is presented. The final paper in the session describes a new algorithm for fast reduced order full-wave models. 55.1 Piece-Wise Approximations of RLCK Circuit Responses using Moment Matching Speaker: Chirayu S. Amin, - Northwestern Univ. Authors:Chirayu S. Amin, , Yehea Ismail- Northwestern Univ., Evanston, IL, , Florentin Dartu- Intel Corp., Hillsboro, OR 55.2 A Quasi-Convex Optimization Approach to Parameterized Model-Order Reduction Speaker: Kin Cheong Sou, - Massachusetts Institute of Tech. Authors:Kin Cheong Sou, Luca Daniel, , Alexandre Megretski- Massachusetts Institute of Tech., Cambridge, MA 55.3s Structure Preserving Reduction of Frequency Dependent Interconnect Speaker: Quming Zhou, - Rice Univ. Authors:Quming Zhou, Kartik Mohanram, , Athanasios C. Antoulas- Rice Univ., Houston, TX 55.4s Segregation by Primary Phase Factors: A Full-Wave Algorithm for Model-Order Reduction Speaker: Thomas J. Klemas, - Massachusetts Institute of Tech. Authors:Thomas J. Klemas, Luca Daniel, , Jacob K. White- Massachusetts Institute of Tech., Cambridge, MA **********************************************************************************