USER TRACK
Advances in System-Level Design and Synthesis
Topic Area:
System-Level and Embedded
Thursday, June 17, 2010
Time: 4:30 PM — 6:00 PM
Location:
208AB
Summary:
This session highlights design practices using high-level synthesis and SystemC/TLM. Designers at TI and Interra demonstrate how architectural exploration aids in designing a complex multi-media subsystem. NEC demonstrates using high-level synthesis to design a complex IP. Engineers from LG Electronics describe how to use ESL tools for SOC optimization. TI presents an approach to integrate software-debugging and user command semantics using a SystemC-based virtual platform. Cadence presents a TLM-driven methodology and case study to bridge the gap between virtual platform models and synthesizable SystemC models. Finally, Intel demonstrates how to visualize/debug TLM-2.0 AT transactions using SCV transaction recording.
Sponsored by:
| Moderator: | David Black - XtremeEDA Corp., Austin, TX |
12U.1 S—
Systematic Architecture Exploration Through High-Level Synthesis
| Speaker: | Raj Mitra - Texas Instruments, Inc., Bangalore, India | | Authors: | Raj Mitra - Texas Instruments, Inc., Bangalore, India | | | Praveen Tiwari - Interra Systems, Inc., Bangalore, India | | | Mahesh Mehendale - Texas Instruments, Inc., Bangalore, India |
12U.2 S—
High-Level Synthesis Design Space Exploration
| Speaker: | Benjamin Carrion Schafer - NEC Corp., Kawasaki, Japan | | Authors: | Benjamin Carrion Schafer - NEC Corp., Kawasaki, Japan | | | Kazutoshi Wakabayashi - NEC Corp., Kawasaki, Japan |
12U.3 S—
A Two-Phased Multi-Media SOC Design Optimization Using ESL Tools
| Speaker: | Hoon Oh - LG Electronics, Republic of Korea | | Authors: | Hoon Oh - LG Electronics, Republic of Korea | | | Youngkil Park - LG Electronics, Republic of Korea | | | Byungchul Hong - LG Electronics, Republic of Korea | | | Chulho Shin - LG Electronics, Republic of Korea | | | Derek Ko - LG Electronics, Republic of Korea |
12U.4 S—
Integrating Software-Debugger on a SystemC-Based Virtual Platform
| Speaker: | Nizamudheen Ahmed - Texas Instruments, Inc., Bangalore, India | | Authors: | Nizamudheen Ahmed - Texas Instruments, Inc., Bangalore, India | | | Gulur Dwarakanath Nagendra - Texas Instruments, Inc., Bangalore, India |
12U.5 S—
Developing Synthesizable IP Modules from TLM 2.0 Descriptions - A TDIP Methodology Case Study
| Speaker: | Christian Sauer - Cadence Design Systems, Inc., Munich, Germany | | Authors: | Christian Sauer - Cadence Design Systems, Inc., Munich, Germany | | | Felice Balarin - Cadence Design Systems, Inc., San Jose, CA |
12U.6 S—
SCV Transaction Recording and It's Application to TLM-2.0 AT Style Performance Modeling
| Speaker: | Zhu Zhou - Intel Corp., Chandler, AZ | | Authors: | Zhu Zhou - Intel Corp., Chandler, AZ | | | Trevor Wieman - Intel Corp., Colorado Springs, CO | | | Atul Kwatra - Intel Corp., Chandler, AZ |
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